Gigascale integration: Is the sky the limit?

IEEE Circuits and Devices Magazine

Volumn 12, Issue 6, 1996, Pages

  Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE;

GIGASCALE INTEGRATION; SWITCHING ENERGY LIMIT; TRANSIT TIME LIMIT;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0030291849     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.544447     Document Type: Review

References (12)

1. The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1994.
2. R.W. Keyes, "Physical Limits in Digital Electronics," Proc. IEEE, Vol. 63, No. 5, pp. 740-767, May 1975.
3. R.W. Keyes, "The Evolution of Digital Electronics Towards VLSI," IEEE JSSC, Vol. SC-14, No. 2, pp. 193-201, April 1979.
4. J.D. Meindl, "Theoretical, Practical and Analogical Limits in ULSI," IEEE IEDM Tech. Dig., pp. 8-13, 1983.
5. J.D. Meindl, "Low Power Microelectronics: Retrospect and Prospect," Proc. IEEE, Vol. 83, No. 4, pp. 619-635, April 1995.
6. A.J. Bhavnagarwala, V.K. De, B. Austin, J.D. Meindl, "Circuit Techniques for Low Power CMOS GSI," 1996 International Symposium on Low Power Electronics and Design: Digest of Technical Papers, pp. 193-196, August 1996.
7. G.A. Sai-Halasz, "Performance Trends in High-End Processors," Proc. IEEE, Vol. 83, No. 1, pp. 20-36. Jan. 1995.
8. H.T. Kung, "Why Systolic Architectures," IEEE Computer, pp. 37-46, Jan. 1982.
9. J. Davis, V.K. De, J.D. Meindl, "Optimal Low Power Interconnect Networks," 1996 Symposium on VLSI Technology: Digest of Technical Papers, pp. 78-79, June 1996.
10. T. Ohmi, "Scientific Semiconductor Manufacturing Based on Ultraclean Processing Concept," Inter. Conf. on Advanced Microelectronic Devices and Processing, pp. 3-22, Sendai, Japan, Mar. 1994.
11. R.W. Keyes, "The Effect of Randomness in the Distribution of Impurity Atoms on FET Thresholds," App. Phys., 8, pp. 251-259, 1975.
12. V.K. De, et al., "Random MOSFET Parameter Fluctuation Limits to Gigascale Integration," Dig. of VLSI Tech. Sym., pp. 198-199, 1996.