A novel DCVS tree reduction algorithm

2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06

Volumn , Issue , 2006, Pages

  Kavehie, Omid ^a   Navi, Keivan ^a   Nikoubin, Tooraj ^a   Rouholamini, Mahnoush ^b  

^a SHAHID BEHESHTI UNIVERSITY   (Iran)

^b Research and Science Center of Hesarak   (Iran)

Author keywords

CAD; Differential cascode voltage switch logic; Ordered binary decision diagrams; Structured logic tree; Transistor count

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; SWITCHING SYSTEMS;

DIFFERENTIAL CASCODE VOLTAGE SWITCH (DCVS); NETWORK DESIGN; ORDERED BINARY DECISION DIAGRAM (OBDD);

CASCADE CONNECTIONS;

EID: 42749106000     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2006.220824     Document Type: Conference Paper

References (13)

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