Place-and-route impact on the security of DPL designs in FPGAs

2008 IEEE International Workshop on Hardware-Oriented Security and Trust, HOST

Volumn , Issue , 2008, Pages 26-32

  Guilley, Sylvain ^a   Chaudhuri, Sumanta ^a   Sauvage, Laurent ^a   Graba, Tarik ^a   Danger, Jean Luc ^a   Hoogvorst, Philippe ^a   Vong, Vinh Nga ^a   Nassar, Maxime ^a  

^a TELECOM PARISTECH   (France)

Author keywords

Backend level countermeasures; Dual rail with precharge logic (DPL); WDDL

Indexed keywords

CRYPTOGRAPHY; ELECTRIC BREAKDOWN; RAILS; THERMOELECTRIC EQUIPMENT;

BACKEND-LEVEL COUNTERMEASURES; CRYPTOGRAPHIC ALGORITHMS; DIFFERENTIAL POWER ANALYSIS; DUAL-RAIL; DUAL-RAIL WITH PRECHARGE LOGIC (DPL); ELECTRONIC DEVICES; INFORMATION HIDING; LOGIC STYLE; MATHEMATICAL STRUCTURES; POWER CONSUMPTION; PROPAGATION DELAYS; PROTECTION STRATEGIES; SECRET KEYS; SIDE CHANNELS; SIDE-CHANNEL ATTACKS; WDDL; WEAK POINTS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 51849095526     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HST.2008.4559042     Document Type: Conference Paper

References (29)

1. P. Kocher, J. Jaffe, and B. Jun, "Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems," in Proceedings of CRYPTO'96, ser. LNCS, vol. 1109, Springer-Verlag, 1996, pp. 104-113, (PDF).
2. _, "Differential Power Analysis," in Proceedings of CRYPTO'99. ser. LNCS, vol. 1666. Springer-Verlag. 1999, pp. pp 388-397. (PDF).
3. F.-X. Standaert, S. B. Örs, and B. Preneel, "Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure?" in CHES, ser. LNCS, vol. 3156. Springer-Verlag, 2004, pp. 30-44.
4. E. Oswald, S. Mangard, N. Pramstaller, and V. Rijmen, "A Side-Channel Analysis Resistant Description of the AES S-box," in Proceedings of FSE'05, ser. LNCS, LNCS, Ed., vol. 3557. Springer, February 2005, pp. 413-423., paris, France.
5. M.-L. Akkar and C. Giraud, "An Implementation of DES and AES Secure against Some Attacks," in Proceedings of CHES'01, ser. LNCS, LNCS, Ed., vol. 2162. Springer, May 2001, pp. 309-318., paris, France.
6. F.-X. Standaert, G. Rouvroy, and J.-J. Quisquater, "FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks," in proceedings of FPL 2006, August 2006, madrid, Spain.
7. D. Suzuki, M. Saeki, and T. Ichikawa, "Random Switching Logic: A Countermeasure against DPA based on Transition Probability," 2004, http://eprint.iacr.org/2004/346.
8. É. Peeters, F.-X. Standaert, N. Donckers, and J.-J. Quisquater, "Improved Higher-Order Side-Channel Attacks with FPGA Experiments," in CHES, ser. LNCS, vol. 3659. Springer, 2005, pp. 309-323.
9. K. Tiri and P. Schaumont, "Changing the odds against Masked Logic," in 13th Annual Workshop on Selected Areas in Cryptography, ser. LNCS, vol. 4356, 2006, pp. 134-146, august 17 & 18, 2006, Montreal, Canada.
10. P. Schaumont and K. Tiri, "Masking and Dual Rail Logic Don't Add Up," in CHES, ser. LNCS, vol. 4727, Springer, 2007, pp. 95-106, vienna, Austria.
11. Z. Chen and P. Schaumont, "Slicing Up a Perfect Hardware Masking Scheme," in HOST, ser. IEEE, 2008, june 9, Anaheim, USA.
12. S. Mangard, N. Pramstaller, and E. Oswald, "Successfully Attacking Masked AES Hardware Implementations," in Proceedings of CHES'05, ser. LNCS, LNCS, Ed., vol. 3659, Springer, September 2005, pp. 157-171., Edinburgh, Scotland, UK.
13. K. Tiri, M. Akmal, and I. Verbauwhede, "A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards," in European Solid-State Circuits Conference (ESSCIRC), September 2002, pp. 403-406, [Online]. Available: http://citeseer.ist.psu.edu/tiri02dynamic.html
14. S. Guilley, P. Hoogvorst, Y. Mathieu, R. Pacalet, and J. Provost, "CMOS Structures Suitable for Secured Hardware," in Proceedings of DATE'04. February 2004, pp. 1414-1415, paris, France.
15. A. Razafindraibe, M. Robert, and P. Maurine, "Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA," in PATMOS, 2007, pp. 340-351, göteborg, Sweden.
16. K. Tiri and I. Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation," in DATE'04. February 2004, pp. 246-251, Paris, France.
17. T. Popp and S. Mangard, "Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints," in Proceedings of CHES'05. ser. LNCS, LNCS, Ed., vol. 3659. Springer, September 2005, pp. 172-186., Edinburgh, Scotland, UK.
18. D. Suzuki and M. Saeki, "Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style," in CHES, ser. LNCS, vol. 4249. Springer, 2006, pp. 255-269, http://dx.doi.org/10.1007/11894063_21.
19. S. Guilley, L. Sauvage, J.-L. Danger, T. Graba, and Y. Mathieu. "Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs." in SSIRI. Yokohama, Japan: IEEE, jul 2008, http://hal.archives-ouvertes.fr/hal-00259153/en/.
20. "Xilinx FPGA designer: http://www.xilinx.com/."
21. "Altera FPGA designer: http://www.altera.com/."
22. ]22] NIST/ITL/CSD. "Data Encryption Standard. FIPS PUB 46-3," Oct 1999, http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf.
23. "Delay and power calculation standards - Part 3: Standard Delay Format (SDF) for the electronic design process," IEC 61523-3 First edition 2004-09; IEEE 1497, pp. 1-94, 2004.
24. K. Tiri and I. Verbauwhede, "Secure Logic Synthesis," in FPL, ser. LNCS, vol. 3203, August 2004, pp. 1052-1056.
25. _, "Place and Route for Secure Standard Cell Design." in Proceedings of WCC/CARDIS, Aug 2004, pp. 143-158. Toulouse, France.
26. S. Guilley, P. Hoogvorst, Y. Mathieu, and R. Pacalet, "The "Backend Duplication" Method," in CHES, vol. LNCS 3659. Springer, 2005, pp. 383-397. August 29th - September 1st, Edinburgh, Scotland, UK.
27. P. Yu and P. Schaumont, "Secure FPGA circuits using controlled placement and routing," in CODES+ISSS'07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis. New York, NY, USA: ACM, 2007, pp. 45-50.
28. "IcTER: integrity and confidentiality in reconfigurable technologies, ANR Non-Thematic project, http://www.lirmm.fr/~w3mic/ANR/," 2006.
29. "SeFPGA: Secure embedded FPGAs, ANR project from call ARFU, http://projects.comelec.enst.fr/sefpga/," 2008.