CMOS structures suitable for secured hardware

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 1414-1415

  Guilley, Sylvain ^a   Hoogvorst, Philippe ^a   Mathieu, Yves ^a   Pacalet, Renaud ^a   Provost, Jean ^a  

^a INSTITUT TELECOM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DATA RANDOMIZATION; MICROELECTRONIC DESIGN; POWER CONSUMPTION; SPICE SIMULATIONS; CMOS STRUCTURES; INFORMATION LEAKAGE; MEMORYLESS; NAND GATE;

COMPUTER SIMULATION; CORRELATION METHODS; CRYPTOGRAPHY; DATABASE SYSTEMS; DECODING; ELECTRIC IMPEDANCE; ENCODING (SYMBOLS); LOGIC GATES; MICROELECTRONICS; TRANSISTORS;

CMOS INTEGRATED CIRCUITS; EXHIBITIONS;

EID: 3042609835     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269113     Document Type: Conference Paper

References (5)

1. P. Kocher, J. Jaffe, and B. Jun. Differential Power Analysis: Leaking secrets. Proc. of CRYPTO'99, 1666:388-397, 1999.
2. S. Moore, R. Anderson, P. Cunningham, R. Mullins, and G. Taylor. Improving smart card security using self-timed circuits. Proc. of Async'02, pages 211-217, 2002.
3. M. Shams, J. Ebergen, and M. Elmasry. Modeling and comparing CMOS implementations of the C-element, IEEE Transactions on VLSI Systems, 6(4):563-567, 1998.
4. I. E. Sutherland. Micropipelines. Communications of the ACM (Turing award), 32(6):720-738, 1989.
5. Z. Yu, S. Furber, and L. Plana. An investigation into the security of self-timed circuits. Proc. of Async'03, 2003.