Implications of rent's rule for NoC design and its fault-tolerance

Proceedings - NOCS 2007: First International Symposium on Networks-on-Chip

Volumn , Issue , 2007, Pages 283-294

  Greenfield, Daniel ^a   Banerjee, Arnab ^a   Lee, Jeong Gun ^a   Moore, Simon ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; FAULT TOLERANCE; MATHEMATICAL MODELS; TELECOMMUNICATION TRAFFIC; VLSI CIRCUITS;

NETWORKS-ON-CHIP (NOC); NOC DESIGN; RENT'S RULE; VLSI DESIGN;

MICROPROCESSOR CHIPS;

EID: 36348965912     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2007.26     Document Type: Conference Paper

References (13)

1. A.E. Caldwell, Yu Cao, Andrew B. Kahng, F. Koushanfar, Hua Lu, I.L. Markov, M. Oliver, D. Stroobandt, and D. Sylvester. GTX: the MARCO GSRC technology extrapolation system. In 37th Design Automation Conference, pages 693-698, June 5-9, 2000.
2. Chun-Lung Chen and Ge-Ming Chiu. A fault-tolerant routing scheme for meshes with nonconvex faults. Parallel and Distributed Systems, IEEE Transactions on, 12(5):467-475, May 2001.
3. A.A. Chien and Jae H. Kim. Planar-adaptive routing: Low-cost adaptive networks for multiprocessors. In Computer Architecture, 1992. Proceedings., The 19th Annual International Symposium on, pages 268-277, May 19-21, 1992.
4. P. Christie and D. Stroobandt. The interpretation and application of rent's rule. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 8(6):639-648, Dec. 2000.
5. R.P. Dick, D.L. Rhodes, and W. Wolf. TGFF: task graphs for free. In Hardware/Software Codesign, 1998. (CODES/CASHE '98) Proceedings of the Sixth International Workshop on, pages 97-101, 15-18 March 1998.
6. W. E. Donath. Wire length distribution for placements of computer logic. In IBM Journal of Research and Development, VLSI Circuit Design, volume 25, page 152, 1981.
7. Erno Salminen Heikki Orsila, Tero Kangas and Timo D. Hamalainen. Parameterizing simulated annealing for distributing task graphs on multiprocessor SoCs. In International Symposium on System-on-Chip 2006, Tampere, Finland, pages pp. 73-76, November 2006.
8. Jingcao Hu and R. Marculescu. Energy-aware mapping for tile-based noc architectures under performance constraints. In Design Automation Conference. Proceedings of the ASP-DAC 2003. Asia and South Pacific, pages 233-239, 21-24 Jan. 2003.
9. Jongman Kim, C. Nicopoulos, and Dongkook Park. A gracefully degrading and energy-efficient modular router architecture for on-chip networks. In 33rd International Symposium on Computer Architecture, pages 4-15, 17-21 June 2006.
10. R. Mullins, A. West, and S. Moore. Low-latency virtual-channel routers for on-chip networks. In Proceedings of the 31st Annual International Symposium on Computer Architecture, pages 188-197, 19-23 June 2004.
11. L.M. Ni and P.K. McKinley. A survey of wormhole routing techniques in direct networks. Computer, 26(2):62-76, Feb. 1993.
12. Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang. The case for a single-chip multiprocessor. SIGOPS Oper. Syst. Rev., 30(5):2-11, 1996.
13. M.B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P Johnson, Jae-Wook Lee, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agarwal. The Raw microprocessor: a computational fabric for software circuits and general-purpose programs. Micro, IEEE, 22(2):25-35, March-April 2002.