Programmable routing tables for degradable torus-based networks on chips

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 1065-1068

  Shahabi, A ^a   Honarmand, N ^a   Navabi, Z ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS; NETWORK ROUTING; PROBLEM SOLVING; SWITCHING; TELECOMMUNICATION LINKS;

NETWORK SWITCHES; NETWORKS ON CHIPS; ROUTING MECHANISM;

INTEGRATED CIRCUITS;

EID: 34548830212     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378193     Document Type: Conference Paper

References (10)

1. R. Saleh et al., "System-on-Chip: Reuse and Integration," Proc. IEEE, vol. 94, no. 6, pp 1050-1069, Jun 2006.
2. L. Benini and O. De Micheli, "Networks on chips: a new SoC paradigm," IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
3. P.P. Pande C. Grecu, A. Ivanov. R. Saleh, and G. De Micheli, "Design, Synthesis, and Test of Network On Chips," IEEE Des. Test. Comput., vol 22. no. 5, pp. 404-413, Sept./Oct. 2005.
4. J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks - An Engineering Approach, Morgan Kaufmann, 2002.
5. W.J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Packet-Switched Interconnections," in proc. DAC'01, 2001, pp. 683-689, 2001.
6. P. P. Pande et al., "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures," IEEE Trans. Comput., vol. 54, no. 8, pp. 1025-1040, Aug. 2002.
7. Semiconductor Industry Association, International Technology Roadmap for Semiconductors, Edition 2005, 2005.
8. N. Honarmand, A.Shahabi, H. Sohofi, M. Abbaspour, and Z. Navabi, "High Level Synthesis of Degradable ASICs Using Virtual Binding," VLSI Test Symposium, 2007, in press.
9. R. Marculescu, "Networks-on-Chip: The Quest for On-Chip Fault-Tolerant Communication", in proc. ISVLSI'03, pp. 8-12, Feb. 2003.
10. M. Yang, T. Li, Y. Jiang, and Y. Yang, "Fault-Tolerant Routing Schemes in RDT(2,2,1)/a-Based Interconnection Network for Networks-on-Chip Designs," in Proc. ISPAN'05, pp. 1-6, Dec. 2005.