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Volumn , Issue , 2007, Pages 15-24

Notes on pulse signaling

Author keywords

[No Author keywords available]

Indexed keywords

SIGNALING;

EID: 51749105814     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/async.2007.23     Document Type: Conference Paper
Times cited : (3)

References (13)
  • 1
    • 0036761283 scopus 로고    scopus 로고
    • Chain: A delay-insensitive chip area interconnect
    • J. Bainbridge and S. Furber. CHAIN: A delay-insensitive chip area interconnect. IEEE Micro, 22:16-23, 2002.
    • (2002) IEEE Micro , vol.22 , pp. 16-23
    • Bainbridge, J.1    Furber, S.2
  • 7
    • 0015995299 scopus 로고
    • Towards a theory of universal speedindependent modules
    • Jan.
    • R. M. Keller. Towards a theory of universal speedindependent modules. IEEE Transactions on Computers, C-23(1):21-33, Jan. 1974.
    • (1974) IEEE Transactions on Computers , vol.C-23 , Issue.1 , pp. 21-33
    • Keller, R.M.1
  • 8
    • 2542433759 scopus 로고    scopus 로고
    • PhD thesis, California Institute of Technology, May, Caltech Computer Science Technical Report 2001.011
    • M. Nyström. Asynchronous Pulse Logic. PhD thesis, California Institute of Technology, May 2001. Caltech Computer Science Technical Report 2001.011.
    • (2001) Asynchronous Pulse Logic
    • Nyström, M.1
  • 12
    • 0037387930 scopus 로고    scopus 로고
    • Low-power synchronous-toasynchronous-to-synchronous interlocked pipelined cmos circuits operating at 3.3-4.5 ghz
    • Apr.
    • S. Schuster and P. Cook. Low-power synchronous-toasynchronous-to- synchronous interlocked pipelined cmos circuits operating at 3.3-4.5 ghz. IEEE Journal of Solid-State Circuits, 38(4):622-630, Apr. 2004.
    • (2004) IEEE Journal of Solid-State Circuits , vol.38 , Issue.4 , pp. 622-630
    • Schuster, S.1    Cook, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.