High-performance noise-robust asynchronous circuits

Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

Volumn 2006, Issue , 2006, Pages 173-178

  Golani, Pankaj ^a   Beerel, Peter A ^a  

^a University of Southern California   (United States)

Author keywords

Asynchronous; Cycle time; Library; Overlap period; Robustness to noise; Worst case crosstalk environment

Indexed keywords

ASYNCHRONOUS STANDARD-CELL LIBRARY; CYCLE TIME; NOISE SENSITIVENESS; OVERLAP PERIOD;

COMPUTER SIMULATION; CROSSTALK; INTEGRATED CIRCUIT LAYOUT; ROBUSTNESS (CONTROL SYSTEMS); SPURIOUS SIGNAL NOISE;

CIRCUIT THEORY;

EID: 33749340079     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2006.51     Document Type: Conference Paper

References (14)

1. P. A. Beerel. Asynchronous Circuits: An Increasingly Practical Design Solution, in ISQED'02 March. 2002.
2. M. Ferretti. Single-track Asynchronous Pipeline Template, Ph.D. Thesis, University of Southern California, Aug. 2004.
3. M. Ferretti, R. O. Ozdag, P. A. Beerel. High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells. ASYNC'04, April, 2004.
4. M. Ferretti and P. A. Beerel. Single-Track Asynchronous Pipeline Templates using 1-of-N Encoding, DATE'02, Mar. 2002.
5. P. Golani and P. A. Beerel. Back-Annotation in High-Speed Asynchronous Design, PATMOS, Sep. 2005.
6. R. O. Ozdag and P. A. Beerel, High Speed QDI Asynchronous Pipelines, ASYNC'02, April 2002.
7. K. van Berkel, and A. Bink, Single-Track Handshake Signaling with Application to Micropipelines and Handshake Circuits, ASYNC'96, pp: 122-133.
8. F. Dantu and L.T. Pileggi. Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling, DAC'97, June 1997
9. K. L. Shepard, Design Methodologies for Noise in Digital Integrated Circuits. DAC'98, June 1998.
10. D. G. Chinnery and K. Keutzer, Closing the Gap between ASIC and Custom: Tools and Techniques for High-Performance ASIC Design, Kluwer Academic Publishers, ISBN 1-4020-7113-2, May 2002.
11. R. O. Ozdag. Template-Based Asynchronous Circuit Design, Ph.D. Thesis, University of Southern California, Nov, 2003.
12. I. E. Sutherland, and S. Fairbanks. GasP: a Minimal FIFO Control, ASYNC'01, March 2001.
13. M. Nyström and A. J. Martin. Asynchronous Pulse Logic. Boston: Kluwer Academic Publishers, 2001.
14. U. Cummings, A. Lines, and A. Martin. An Asynchronous Pipelined Lattice Structure Filters, ASYNC'94, March 1994.