High performance asynchronous asic back-end design flow using single-track full-buffer standard cells

Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 10, Issue , 2004, Pages 95-105

  Ferretti, Marcos ^a   Ozdag, Recep O ^a   Beerel, Peter A ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BUFFER CIRCUITS; COMPUTER SIMULATION; DATA PROCESSING; DELAY CIRCUITS; DIGITAL LIBRARIES; ENCODING (SYMBOLS); OPTIMIZATION; TRANSISTORS;

ASYNCHRONOUS CHANNELS; ASYNCHRONOUS DESIGN; QUASI-DELAY-INSENSITIVE (QDI) TEMPLATES; SINGLE-TRACK FULL-BUFFER STANDARD CELLS;

CMOS INTEGRATED CIRCUITS;

EID: 2942670415     PISSN: 15228681     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

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