Low-power synchronous-to-asynchronous-to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 4, 2003, Pages 622-630

  Schuster, Stanley E ^a   Cook, Peter W ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Asynchronous; Digital circuits; High speed; Low power

Indexed keywords

ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; SEMICONDUCTOR SWITCHES; TIMING CIRCUITS;

ASYNCHRONOUS; HIGH SPEED; INTERLOCKED PIPELINED CMOS CIRCUITS; LOW POWER;

CMOS INTEGRATED CIRCUITS;

EID: 0037387930     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.809512     Document Type: Article

References (10)

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