Primitive-level pipelining method on delay-insensitive model for RSFQ pulse-driven logic

Proceedings - 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 1998-March, Issue , 1998, Pages 262-273

  Kameda, Yoshio ^a   Polonsky, Stanislav ^b   Maezawa, Masaaki ^c   Nanya, Takashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b STONY BROOK UNIVERSITY   (United States)

^c ELECTROTECHNICAL LABORATORY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; DIGITAL STORAGE;

BINARY INFORMATION; BINARY OPERATIONS; DELAY-INSENSITIVITY; INTERCONNECT DELAY; PIPELINE REGISTERS; RAPID SINGLE-FLUX QUANTUM; STORAGE CAPABILITY; VERIFICATION TOOLS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 33846428289     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1998.666511     Document Type: Conference Paper

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