Fast custom instruction identification by convex subgraph enumeration

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2008, Pages 1-6

  Atasu, Kubilay ^a   Mencer, Oskar ^a   Luk, Wayne ^a   Özturan, Can ^b   Dündar, Günhan ^b  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b BOGAZICI UNIVERSITY   (Turkey)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC SYSTEMS; CUSTOM INSTRUCTION; INTERNATIONAL CONFERENCES;

CRYPTOGRAPHY; DATA FLOW ANALYSIS; HIGH LEVEL LANGUAGES; MULTIMEDIA SYSTEMS; SILICON; SPACE RESEARCH;

BENCHMARKING;

EID: 51649113423     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2008.4580145     Document Type: Conference Paper

References (16)

1. Ilog cplex. http://www.ilog.com/products/cplex/.
2. lpsolve. http://sourceforge.net/projects/lpsolve.
3. Trimaran. http://www.trimaran.org.
4. K. Atasu et al. Optimizing instruction-set extensible processors under data bandwidth constraints. In DATE, pages 588-593, Nice, France, Apr. 2007.
5. K. Atasu, G. Dündar, and C. Özturan. An integer linear programming approach for identifying instruction-set extensions. In CODES+ISSS 2005, Jersey City, NJ, Sept. 2005.
6. K. Atasu, L. Pozzi, and P. Ienne. Automatic application-specific instruction-set extensions under microarchitectural constraints. In 40th DAC, Anaheim, CA, June 2003.
7. P. Bonzini and L. Pozzi. Polynomial-time subgraph enumeration for automated instruction set extension. In DATE, pages 1331-1336, Nice, France, Apr. 2007.
8. N. Clark, H. Zhong, and S. Mahlke. Processor acceleration through automated instruction set customization. In MICRO, San Diego, CA, Dec. 2003.
9. J. Cong, Y. Fan, G. Han, and Z. Zhang. Application-specific instruction generation for configurable processor architectures. In FPGA 2004, Monterey, CA, Feb. 2004.
10. R. M. Garey and D. S. Johnson. Computers and Intractability; A Guide to the Theory of NP-Completeness. W. H. Freeman and Co., New York, 1979.
11. R. Leupers et al. A design flow for configurable embedded processors based on optimized instruction set extension synthesis. In DATE 2006, Munich, Germany, Mar. 2006.
12. N. Pothineni, A. Kumar, and K. Paul. Application specific datapath with distributed I/O functional units. In VLSI Design, pages 551-558, Hyderabad, India, Jan. 2007.
13. L. Pozzi and P. Ienne. Exploiting pipelining to relax register-file port constraints of instruction-set extensions. In CASES 2005, San Francisco, CA, Sept. 2005.
14. F. Sun, S. Ravi, A. Raghunathan, and N. Jha. A scalable application-specific processor synthesis methodology. In ICCAD, pages 283-290, San Jose, CA, Nov. 2003.
15. A. K. Verma, P. Brisk, and P. Ienne. Rethinking custom ise identification: A new processor-agnostic method. In CASES, pages 125-134, Salzburg, Austria, Sept. 2007.
16. P. Yu and T. Mitra. Scalable custom instructions identification for instruction-set extensible processors. In CASES 2004, Washington, DC, Sept. 2004.