A Scalable Application-Specific Processor Synthesis Methodology

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 283-290

  Sun, Fei ^a   Ravi, Srivaths ^b   Raghunathan, Anand ^b   Jha, Niraj K ^a  

^a Princeton University   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; INTELLECTUAL PROPERTY; LOGIC DESIGN; MICROPROCESSOR CHIPS; PROGRAM COMPILERS;

FLEXIBLE INSTRUCTION PROCESSORS (FIP); LOCAL TARGET AREA (LTA); VERILOG CODES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0348040125     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159702     Document Type: Conference Paper

References (28)

1. Xtensa microprocessor, Tensilica Inc. (http://www.tensilica.com).
2. Jazz DSP, Improv Systems Inc. (http://www.improvsys.com).
3. DSP core, 3DSP Corp. (http://www.3dsp.com).
4. A R Ctangent processor, Arc International (http://www.arc.com).
5. J. A. Fisher, "Customized instruction sets for embedded processors," in Proc. Design Automation Conf., June 1999, pp. 253-257.
6. K. Keutzer, S. Malik, and A. R. Newton, "From ASIC to ASIP: The next design discontinuity," in Proc. Int. Conf. Computer Design, Sept. 2002, pp. 84-90.
7. D. Fischer, J. Teich, M. Thies, and R. Weper, "Efficient architecture/compiler co-exploration for ASIPs," in Proc. Int. Conf. Compilers, Architecture, and Synthesis for Embedded Systems, Oct. 2002, pp. 27-34.
8. D. Kirovski, C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "Application-driven synthesis of core-based systems," in Proc. Int. Conf. Computer-Aided Design, Nov. 1997, pp. 104-107.
9. K. Kucukcakar, "An ASIP design methodology for embedded systems," in Proc. Int. Symp. HW/SW Codesign, May 1999, pp. 17-21.
10. M. Knieser and C. Papachristou, "COMET: A hard ware-soft ware code-sign methodology," in Proc. European Design Automation Conf., Sept. 1996, pp. 178-183.
11. S. P. Seng, W. Luk, and P. Y. K. Cheung, "Flexible instruction processors," in Proc. Int. Conf. Compilers, Architecture, and Synthesis for Embedded Systems, Nov. 2000, pp. 193-200.
12. R. Schreiber, S. Aditya, S. Mahlke, V. Kathail, B. R. Rau, D. Cron-quist, and M. Sivaraman, "PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators," Tech. Rep., HP Laboratories, Palo Alto, 2001.
13. C. Alippi, W. Fornaciari, L. Pozzi, and M. Sami, "A DAG-based design approach for reconfigurable VLIW processors," in Proc. Design Automation & Test Europe Conf., Mar. 1999, pp. 778-779.
14. H. Choi, J. H. Yi, J.-Y. Lee, I.-C. Park, and C.-M. Kyung, "Exploiting intellectual properties in ASIP designs for embedded DSP software," in Proc. Design Automation Conf., June 1999, pp. 939-944.
15. N. Moreano, G. Araujo, Z. Huang, and S. Malik, "Datapath merging and interconnection sharing for reconfigurable architectures," in Proc. Int. Symp. System Synthesis, Nov. 2002, pp. 38-43.
16. T.V.K Gupta, R. Ko, and R. Barua, "Compiler-directed customization of ASIP cores," in Proc. Int. Symp. HW/SW Codesign, May 2002, pp. 97-102.
17. M. Arnold and H. Corporaal, "Designing domain-specific processors," in Proc. Int. Symp. HW/SW Codesign, Apr. 2001, pp. 61-66.
18. H. Choi, J.-S. Kim, C.-W. Yoon, I.-C. Park, S. H. Hwang, and C.-M. Kyung, "Synthesis of application specific instructions for embedded DSP software," IEEE Trans. Computers, vol. 48, no. 6, pp. 603-614, June 1999.
19. J. E. Lee, K. Choi, and N. Dutt, "Efficient instruction encoding for automatic instruction set design of configurable ASIPs," in Proc. Int. Conf. Computer-Aided Design, Nov. 2002, pp. 649-654.
20. F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "Synthesis of custom processors based on extensible platforms," in Proc. Int. Conf. Computer-Aided Design, Nov. 2002, pp. 641-648.
21. K. Atasu, L. Pozzi, and P. Ienne, "Automatic application-specific instruction-set extensions under microarchitectural constraints," in Proc. Design Automation Conf., June 2003, pp. 256-261.
22. N. Cheung, J. Henkel, and S. Parameswaran, "Rapid configuration & instruction selection for an ASIP: A case study," in Proc. Design Automation & Test Europe Conf., Mar. 2003, pp. 802-807.
23. N. Clark, W. Tang, and S. Mahlke, "Automatically generating custom instruction set extensions," in Proc. Wkshp. Application Specific Processors, Nov. 2002.
24. R. P. Wilson, R. S. French, C. S. Wilson, S. P. Amarasinghe, J. A. M. Anderson, S. W. K. Tjiang, S. W. Liao, C. W. Tseng, M. W. Hall, M. S. Lam, and J. L. Hennessy, "SUIF: An infrastructure for research on parallelizing and optimizing compilers," SIGPLAN Notices, vol. 29, no. 12, pp. 31-37, 1994.
25. T. Callahan and J. Wawrzynek, "Simple profiling system for SUIF," in Proc. The First SUIF Compiler Wkshp., Jan. 1996.
26. J. B. Fenwick Jr. and L. L. Pollock, "Implementing an optimizing Linda compiler using SUIF," in Proc. The. First SUIF Compiler Wkshp., Jan. 1996.
27. Design Compiler, Synopsys Inc. (http://www.synopsys.com).
28. CB-11 Cell Based IC Product Family, NEC Electronics, Inc. (http://www.necel.com).