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Volumn , Issue , 2008, Pages 306-309

A comparative study of reliability and performance of strain engineering using CESL stressor and mechanical strain

Author keywords

[No Author keywords available]

Indexed keywords

HYDROGEN; NITRIDES; SEMICONDUCTOR QUANTUM DOTS; STRESSES;

EID: 51549104118     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2008.4558902     Document Type: Conference Paper
Times cited : (10)

References (9)
  • 1
    • 4544357717 scopus 로고    scopus 로고
    • Delaying forever : Uniaxial strained silicon transistors in a 90nm CMOS technology, in VLSI symp
    • K. Mistry, et al., "Delaying forever : Uniaxial strained silicon transistors in a 90nm CMOS technology," in VLSI symp. Tech. Dig., 2004, p.50-51.
    • (2004) Tech. Dig , pp. 50-51
    • Mistry, K.1
  • 2
    • 4544320963 scopus 로고    scopus 로고
    • Understanding Stress Enhanced Performance in Intel 90nm CMOS Technology, in VLSI Symp
    • M.D.Giles, et al., "Understanding Stress Enhanced Performance in Intel 90nm CMOS Technology," in VLSI Symp. Tech. Dig., 2001, p. 118-119.
    • (2001) Tech. Dig , pp. 118-119
    • Giles, M.D.1
  • 3
    • 21644452652 scopus 로고    scopus 로고
    • Dual Stress Liner for High Performance sub45nm Gate Length SOl CMOS Manufacturing
    • H.S.Yang, et al., "Dual Stress Liner for High Performance sub45nm Gate Length SOl CMOS Manufacturing," in IEDM Tech. Dig., 2004, p.1075-1078.
    • (2004) IEDM Tech. Dig , pp. 1075-1078
    • Yang, H.S.1
  • 4
    • 41149095123 scopus 로고    scopus 로고
    • High-performance low operation power transistor for 45 nm node universal applications, in VLSI Symp
    • M. Shima, et al., "High-performance low operation power transistor for 45 nm node universal applications," in VLSI Symp. Tech. Dig., 2006, p. 15-157.
    • (2006) Tech. Dig , pp. 15-157
    • Shima, M.1
  • 5
    • 34447264710 scopus 로고    scopus 로고
    • Stress proximity technique for performance improvement with dual stress liner at 45 nm technology and beyond, in VLSI Symp
    • X. Chen, et al., "Stress proximity technique for performance improvement with dual stress liner at 45 nm technology and beyond," in VLSI Symp. Tech. Dig., 2006, p. 60-61.
    • (2006) Tech. Dig , pp. 60-61
    • Chen, X.1
  • 6
    • 41149150331 scopus 로고    scopus 로고
    • 1-D and 2-D geometry effects in uniaxially-strained dual etch stop layer stressor integrations, in VLSI Symp
    • P. Grudowski, et al., "1-D and 2-D geometry effects in uniaxially-strained dual etch stop layer stressor integrations," in VLSI Symp. Tech. Dig., 2006, p. 62-63.
    • (2006) Tech. Dig , pp. 62-63
    • Grudowski, P.1
  • 7
    • 0034452586 scopus 로고    scopus 로고
    • Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design
    • S. Ito, et al., "Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design," in IEDM Tech. Dig., 2000, p.247-250.
    • (2000) IEDM Tech. Dig , pp. 247-250
    • Ito, S.1
  • 8
    • 46049084627 scopus 로고    scopus 로고
    • A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET utilizing Si (110) Channel for Both N and PMOSFETs
    • C. Y. Kang, et al., "A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET utilizing Si (110) Channel for Both N and PMOSFETs," in IEDM Tech. Dig., 2006, p. 1-4.
    • (2006) IEDM Tech. Dig , pp. 1-4
    • Kang, C.Y.1
  • 9
    • 33847721005 scopus 로고    scopus 로고
    • Negative Bias Temperature Instability of Carrier-Transport Enhanced pMOSFET with Performance Boosters
    • H.S. Rhee, et al., "Negative Bias Temperature Instability of Carrier-Transport Enhanced pMOSFET with Performance Boosters," in IEDM Tech. Dig., 2005, p.692-695.
    • (2005) IEDM Tech. Dig , pp. 692-695
    • Rhee, H.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.