High Fan-in Dynamic CMOS Comparators with Low Transistor Count

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 50, Issue 9, 2003, Pages 1216-1220

  Wang, Chua Chin ^a   Lee, Po Ming ^a   Wu, Chi Feng ^b   Wu, Hsin Long ^a  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b Wafer Test Fact Philips S   (Taiwan)

Author keywords

Build in self test (BIST); Dynamic comparator; High fan in; Testing; Zero one detector

Indexed keywords

ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; TRANSISTORS;

DYNAMIC COMPARATOR;

CMOS INTEGRATED CIRCUITS;

EID: 0141638642     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.816338     Document Type: Article

References (10)

1. C.-C. Wang, C.-F. Wu, S.-H. Chen, and C.-H. Kao, "In sawing lanes multilevel BIST for known good dies of LCD drivers," Electron. Lett., vol. 35, no. 84, pp. 1543-154, 1999.
2. L. T. Clark and G. F. Taylor, "High fan-in circuit design," IEEE J. Solid-State Circuits, vol. 31, pp. 91-96, Jan. 1996.
3. V. Fried and S. Liu, "Dynamic logic CMOS circuit," IEEE J. Solid-State Circuits, vol. SC-19, pp. 263-266, Apr. 1984.
4. N. F. Conclaves and H. J. DeMan, "NORA: A racefree dynamic CMOS technique for pipelined logic structures," IEEE J. Solid-State Circuits, vol. SC-18, pp. 261-266, June 1983.
5. N. H. E. Weste and K. Eshraghian, Principle of CMOS VLSI Design a System Perspective. Reading, MA: Addison Wesley, 1993.
6. C.-F. Wu, C.-C. Wang, R.-T. Hwang, and C.-H. Kao, "IDDQ testable configuration for PLA's by transformation into inverters," in Proc. Int. Symp. Integrated Circuit Technology Systems and Applications, Sept. 1997, pp. 398-401.
7. A. J. van de Goor, Testing Semiconductor Memories Theory and Practice. New York: Wiley, 1994.
8. C.-C. Wang, C.-F. Wu, and K.-C. Tsai, "A 1.0 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking," in Proc. Inst. Elect. Eng. - Comput., Digital Tech., vol. 145, 1998, pp. 433-436.
9. M. Afghahi, "A robust single phase clocking for low power, high-speed VLSI application." IEEE J. Solid-State Circuits, vol. 31, pp. 247-253, Feb. 1996.
10. R. X. Gu and M. I. Elmasry, "All-N-logic high-speed true-single-phase dynamic CMOS logic." IEEE J. Solid-State Circuits, vol. 31. pp. 221-229, Feb. 1996.