Arbitrary long digit integer sorter HW/SW co-design

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 538-543

  Cheng, Shun Wen ^a  

^a TAMKANG UNIVERSITY   (Taiwan)

Author keywords

HW SW co design; Radix Sort; Reusable Embedded Cores; Sorting; System on a Chip (SoC); Technology Independent Methodologies; VLSI design

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; DESIGN; EMBEDDED SYSTEMS; HARDWARE-SOFTWARE CODESIGN; PROGRAMMABLE LOGIC CONTROLLERS; RECONFIGURABLE HARDWARE; SECURITY OF DATA; SORTING; SYSTEM-ON-CHIP;

EMBEDDED CORES; HW/SW CODESIGN; RADIX SORT; SYSTEM ON A CHIP; TECHNOLOGY INDEPENDENT; VLSI DESIGN;

INTEGRATED CIRCUIT DESIGN;

EID: 8844272834     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195075     Document Type: Conference Paper

References (24)

1. M. Afghahi, "A 512 16-b Bit-serial Sorter Chip," IEEE J. Solid-State Circuits, vol. 26, pp. 1452-1457, Oct. 1991.
2. B. Ahn and J. M. Murray, "A Pipelined, Expandable VLSI Sorting Engine Implemented in CMOS Technology," in Proc. IEEE Int'l. Symp. on Circuits and Systems, 1989, pp. 134-137.
3. S. G. Akl, Parallel Sorting Algorithms. Reading, New York: Academic Press, 1985.
4. K. E. Batcher, "Sorting Networks and Their Applications," in Proc. AFIPS 1968 Spring Joint Computer Conference, pp. 307-314, Apr. 1968.
5. G. Baudet and D. Stevenson, "Optimal Sorting Algorithms for Parallel Computer," IEEE Trans. Computers, vol. 27, pp.84-87, Jan. 1978.
6. R. Beigel and J.Gill, "Sorting n Objects with a k-sorter," IEEE Trans. Computers, vol. 39, pp.714-716, May 1990.
7. G. Bilardi and F. P. Preparata, "A Minimum Area VLSI Network for O(log n) Time Sorting," IEEE Trans. Computers, vol. 34, pp.336-343, May 1985.
8. T. C. Chen, Vincent Y. Lum, and C. Tung, "The Rebound Sorter: An Efficient Sort Engine for Large File," in IEEE Proc. 4th Int'l Conf. on Very Large Data Bases, pp. 312-318, Sep. 1978.
9. R. Cole and A. R. Seigel, "Optimal VLSI Circuits for Sorting," JACM, vol. 35, pp.777-809, 1988.
10. Edward. H. Friend, "Sorting on Electronic Computer Systems," JACM, vol. 3, pp.134-168, 1956.
11. C. A. R. Hoare, "Quicksort," Computing Journal, vol. 5, pp. 10-15, 1962.
12. M. Keating and P. Bricaud, Reuse Methodology Manual. Reading: Kluwer, 1998.
13. D. E. Knuth, The Art of Computer Programming, Vol 3: Sorting and Searching. Reading: Addison-Wesley, 1973.
14. J.-G. Lee and B.-G. Lee, "Realization of Large-scale Distributors Based on Batcher Sorters," IEEE Trans. Communications, vol. 47, pp. 1103-1110, July 1999.
15. T. Leighton, "Tight Bounds on The Complexity of Parallel Sorting," IEEE Trans. Computers, vol. 34, pp. 344-354, Apr. 1985.
16. G. S. Miranker, Luong Tang, and Chak-Kuen Wong, "A 'Zero-Time' VLSI Sorter," IBM J. Research & Development, vol. 27, pp. 140-148, Mar. 1983.
17. S. Olariu, M. C. Pinotti, and S. Q. Zheng, "How to Sort N Items Using a Sorting Network of Fixed I/O Size," IEEE Trans. Parallel and Distributed Sys., vol. 10, pp 487-499, May 1999.
18. B. Parhami and D.-M. Kwai, "Data-driven Control Scheme for Linear Arrays: Application to a Stable Insertion Sorter," IEEE Trans. Parallel and Distributed Sys., vol. 10, pp 23-28, Jan. 1999.
19. H. S. Stone, "Parallel Processing with the Perfect Shuffle," IEEE Trans. Computers, vol. 20, pp. 153-161, Feb. 1971.
20. C. D. Thompson, "Area-Time Complexity for VLSI," in Proc. 11th Annual ACM Symp. on Theory of Comp., pp. 81-88, Apr. 1979.
21. C. D. Thompson, "The VLSI Complexity of Sorting," IEEE Trans. Computers, vol. 32, pp.1171-1184, Dec. 1983.
22. N. H. E. Weste and K. Eshraghian, Principle of CMOS VLSI Design, 2nd Ed., Reading: Addison-Wesley, 1993.
23. H. Yasuura, N. Takagi, and S. Yajima, "The Parallel Enumeration Sorting Scheme for VLSI," IEEE Trans. Computers, vol. 31, pp.1192-1201, Dec. 1982.
24. S. Q. Zheng, S. Olariu, and M. C. Pinotti, "A Systolic Architecture for Sorting an Arbitrary Number of Elements," in Proc. 1997 3rd Int. Conf. Algorithms and Architectures for Parallel Processing, pp. 113-126, 1997.