Hierarchical built-in self-testing and FPGA based healing methodology for system-on-a-chip

Proceedings - 2007 NASA/ESA Conference on Adaptive Hardware and Systems, AHS-2007

Volumn , Issue , 2007, Pages 717-724

  Venishetti, Sandeep K ^a   Akoglu, Ali ^a   Kalra, Rahul ^a  

^a University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILDING COMPONENTS; CHLORINE COMPOUNDS; COMPUTER NETWORKS; ERROR ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; MECHANISMS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS;

BUILT-IN SELF-TESTING; HARDWARE OVERHEADS; MICRO ARCHITECTURES; VLSI TECHNOLOGIES;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 50949114696     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHS.2007.59     Document Type: Conference Paper

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