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Volumn 7, Issue 3, 2008, Pages 124-127

Capacitance variability of short range interconnects

Author keywords

6T SRAM; Capacitance; Interconnect; Standard cell; Variability

Indexed keywords

COMPUTER NETWORKS; ELECTRIC BATTERIES; ELECTRON BEAM LITHOGRAPHY; FORECASTING; INTEGRATED CIRCUITS; NANOTECHNOLOGY; PHOTORESISTS; ROUGHNESS MEASUREMENT;

EID: 50949106176     PISSN: 15698025     EISSN: 15728137     Source Type: Journal    
DOI: 10.1007/s10825-007-0154-6     Document Type: Article
Times cited : (8)

References (10)
  • 1
    • 30344447576 scopus 로고    scopus 로고
    • Integrating intrinsic parameter fluctuation description into BSIMSOI to forecast sub-15nm UTB SOI based 6T SRAM operation
    • Samsudin, K., Cheng, B., Brown, A.R., Roy, S., Asenov, A.: Integrating intrinsic parameter fluctuation description into BSIMSOI to forecast sub-15nm UTB SOI based 6T SRAM operation. Solid State Electron. 50, 86 (2006)
    • (2006) Solid State Electron. , vol.50 , pp. 86
    • Samsudin, K.1    Cheng, B.2    Brown, A.R.3    Roy, S.4    Asenov, A.5
  • 2
    • 0042850597 scopus 로고    scopus 로고
    • Interconnect opportunities for gigascale integration
    • Meindl, J.D.: Interconnect opportunities for gigascale integration. IEEE Micro 23 (3), 28-35 (2003)
    • (2003) IEEE Micro , vol.23 , Issue.3 , pp. 28-35
    • Meindl, J.D.1
  • 3
    • 0001013074 scopus 로고    scopus 로고
    • Nanometer-scale linewidth fluctuations caused by polymer aggregates in resist films
    • Yamaguchi, T., Namatsu, H., Nagase, M., Yamazaki, K., Kurihara, K.: Nanometer-scale linewidth fluctuations caused by polymer aggregates in resist films. Appl. Phys. Lett. 71(16), 2388-2390 (1997)
    • (1997) Appl. Phys. Lett. , vol.71 , Issue.16 , pp. 2388-2390
    • Yamaguchi, T.1    Namatsu, H.2    Nagase, M.3    Yamazaki, K.4    Kurihara, K.5
  • 7
    • 0042532317 scopus 로고    scopus 로고
    • Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness
    • Asenov, A., Kaya, S., Brown, A.R.: Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness. IEEE Tran. Electron. Dev. 50(5), 1254-1260 (2003)
    • (2003) IEEE Tran. Electron. Dev. , vol.50 , Issue.5 , pp. 1254-1260
    • Asenov, A.1    Kaya, S.2    Brown, A.R.3
  • 9
    • 25144459947 scopus 로고    scopus 로고
    • Simulation of parasitic interconnect capacitance for present and future ICs
    • Tosik, G., Lisik, Z., Langer, M., Wozny, J.: Simulation of parasitic interconnect capacitance for present and future ICs. Proc. Int. Conf. Comp. Sci. 3514, 607-614 (2005)
    • (2005) Proc. Int. Conf. Comp. Sci. , vol.3514 , pp. 607-614
    • Tosik, G.1    Lisik, Z.2    Langer, M.3    Wozny, J.4
  • 10
    • 0032631519 scopus 로고    scopus 로고
    • Improved VLSI interconnect
    • Cumming, D.R.S.: Improved VLSI interconnect. Int. J. Electron. 86 (8), 957-965 (1999)
    • (1999) Int. J. Electron. , vol.86 , Issue.8 , pp. 957-965
    • Cumming, D.R.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.