High-level power modeling of CPLDs and FPGAs

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 46-51

  Shang, L ^a   Jha, N K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; LOGIC DEVICES; VLSI CIRCUITS;

COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035177116     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

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7. Power modelling for high-level power estimation
8. Power-dissipation driven FPGA place and route under timing constraints
9. Design of a low energy FPGA
10. A probabilistic power prediction tool for the Xilinx 4000-series FPGA
11. Statistical sampling and regression analysis for RT-level power evaluation