Trends in low power digital system-on-chip designs

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 373-378

  Saleh, R ^a   Lim, G ^a   Kadowaki, T ^a   Uchiyama, K ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

Acceleration; Chip scale packaging; Design methodology; Logic design; Logic devices; Personal digital assistants; Power dissipation; Power systems; Productivity; System on a chip

Indexed keywords

ACCELERATION; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHIP SCALE PACKAGES; DESIGN; DIGITAL DEVICES; ELECTRIC LOSSES; ENERGY DISSIPATION; LEAKAGE CURRENTS; LOGIC DESIGN; LOGIC DEVICES; MICROPROCESSOR CHIPS; PERSONAL DIGITAL ASSISTANTS; PRODUCTIVITY; PROGRAMMABLE LOGIC CONTROLLERS; STANDBY POWER SYSTEMS; SYSTEM-ON-CHIP;

CHIP-SCALE PACKAGING; CONSTRAINED MODELS; DESIGN METHODOLOGY; LEAKAGE POWER MANAGEMENT; LOW-POWER DEVICES; LOW-POWER SYSTEMS; SYSTEM ON A CHIP; TECHNOLOGY CHARACTERISTICS;

INTEGRATED CIRCUIT DESIGN;

EID: 84948454728     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996775     Document Type: Conference Paper

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