A True Single-Phase-Clock Dynamic CMOS Circuit Technique

IEEE Journal of Solid-State Circuits

Volumn 22, Issue 5, 1987, Pages 899-901

  Ji Ren, Yuan ^a   Karlsson, Ingemar ^a   Svensson, Christer ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS - SWITCHING;

COMPLEMENTARY MOS (CMOS); SIMPLE CLOCK DISTRIBUTION; SINGLE-PHASE-CLOCK DYNAMIC CMOS CIRCUIT;

INTEGRATED CIRCUITS;

EID: 0023436314     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1987.1052831     Document Type: Article

References (9)

1. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.
2. N Weste and K. Eshraghian, CMOS VLSI Design. Reading, MA: Addison-Wesley, 1985.
3. D. J. Myers and P. A. Ivey, “A design style for VLSI CMOS,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 741–745, 1985.
4. N. F. Goncalves and H. J. De Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” IEEE J Solid-State Circuits, vol. SC-18, pp. 261–266, 1983.
5. C. Svensson, “Clocking of CMOS VLSI systems,” Linkoping Univ., Linkoping, Sweden, Rep. LiTH-IFM-IS-126, 1986.
6. G. Moegen, “Komplementar-MOS-Schaltungstechnik,” in Grossintegration, B. Hofflinger, Ed. Munchen: Oldenburg, 1978, pp. 252–274.
7. B. Sikstrom and L. Wanhammar, “A shift accumulator for signal processing applications,” in Proc. European Conf. Circuit Theory and Design, ECCTD’81 (The Hague, The Netherlands), 1981, pp 919–924.
8. R. Sundblad and C. Svensson, “Fully dynamic switch-level simulation of CMOS circuits,” IEEE Trans. Computer-Aided Des., vol. CAD-6, pp. 282–289, 1987.
9. Gould AMI Semiconductors, Santa Clara, CA, Document 4510033, 1984.