Increasing the throughput of an adaptive router in Network-on-Chip (NoC)

CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis

Volumn , Issue , 2006, Pages 82-87

  Lee, Seung Eun ^a   Bagherzadeh, Nader ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Adaptive router; Chip multiprocessor; Interconnection network; Network on Chip (NoC); Wormhole routing

Indexed keywords

BANDWIDTH; DECISION THEORY; INTERCONNECTION NETWORKS; LOGIC DESIGN; MICROPROCESSOR CHIPS;

ADAPTIVE ROUTER; DECISION TIME; NETWORK-ON-CHIP (NOC); WORMHOLE ROUTING;

ROUTERS;

EID: 34547154253     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176254.1176276     Document Type: Conference Paper

References (15)

1. W. J. Dally and B. Towles. Route Packets, Not Wires: On-chip Interconnection Networks. In Proc. of the 38th Annual conference on Design Automation (DAC'01), pages 684-689, June"2001.
2. L. Benini and G. D. Micheli. Networks on Chips: A New SoC Paradigm. IEEE Computer, 35(1):70-78, 2002.
3. H. Sullivan and T. R. Bashkow. A Large Scale, Homogeneous Fully Distributed Parallel Machine. In Proc. of the 4th annual ACM Symp. on Computer Architecture(ISCA'77), pages 105-117, 1977.
4. T. Nesson and S. L. Johnsson. ROMM Routing on Mesh and Torus Networks. In Proc. of the 7th Annual ACM Symposium on Parallel Algorithms and Architectures(SPAA'95), pages 275-287, 1995.
5. D. Seo, A. Ali, W. Lim and N. Rafique. Near Optimal Worst-case Throughput Routing for Two-Dimensional Mesh Networks. In Proc. of the 32nd Annual Int'l Symposium on Computer Architecture(ISCA'05), pages 432-443, 2005.
6. J. Hu and R. Marculescu. DyAD: Smart Routing for Networks-on-Chip. In Proc. of the 41st Annual conference on Design Automation (DAC'04), pages 260-263, 2004.
7. W. Dally and C. L. Seitz. Deadlock-free Message Routing in Multiprocessor Interconnection Networks. IEEE Trans. on Computer., C-36(5):547-553, 1987.
8. J. Duato. A New Theory of Deadlock-free Adaptive Routing in Wormhole Networks. IEEE Trans. on Parallel and Distributed Systems, 4(12):1320-1331, 1993.
9. G. Chiu. The Odd-Even Turn Model for Adaptive Routing. IEEE Trans. on Parallel and Distributed Systems, 11(7):729-738, 2000.
10. C. J. Glass and L. M. Ni. Adaptive Routing in Mesh-connected Networks. In Proc of the 12th Int'l Conference on Distributed Computing Systems(ICDCS'92), pages 12-19, June 1992.
11. C. J. Glass and L. M. Ni. The Turn Model for Adaptive Routing. Journal of the ACM, 41(5):874-902, 1994.
12. V. Puente, et al. Adaptive Bubble Router: A Design to Improve Performance in Torus Networks. In Proc. of the 28th Int'l Conference on Parallel Processing(ICPP'99), pages 58-67, Sept. 1999.
13. S. J. Lee, K. LEE and H. J. Yoo. Analysis and Implementation of Practical, Cost-effective Networks on Chips. IEEE Design & Test of Computers, 22(5):422-433, 2005.
14. K. Goossens, J. Dielissen and A. Radulescu. Æthereal Network on Chip: Concepts, Architectures, and Implementations. IEEE Design & Test of Computers, 22(5):414-421, 2005.
15. W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufman, San Francisco, 2004.