메뉴 건너뛰기




Volumn , Issue , 2007, Pages 2774-2777

High read stability and low leakage cache memory cell

Author keywords

Low leakage; Noise immunity; Process variations; Read stability; SRAM; Static noise margin

Indexed keywords

CONVERGENCE OF NUMERICAL METHODS; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; STATIC RANDOM ACCESS STORAGE;

EID: 34548828285     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378628     Document Type: Conference Paper
Times cited : (44)

References (11)
  • 1
    • 0036542680 scopus 로고    scopus 로고
    • T SRAM Cells with Full-Swing Single-Ended Bit Line Sensing for On-Chip Cache
    • April
    • T SRAM Cells with Full-Swing Single-Ended Bit Line Sensing for On-Chip Cache," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 2, pp. 91-95, April 2002.
    • (2002) IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.10 , Issue.2 , pp. 91-95
    • Hamzaoglu, F.1
  • 4
    • 0035308547 scopus 로고    scopus 로고
    • The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability
    • April
    • A. Bhavnaganwala, X. Tang, and J. D. Meindl, "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," IEEE Journal of Solid-State Circuits, Vol. 36, No. 4, pp. 658-665, April 2001.
    • (2001) IEEE Journal of Solid-State Circuits , vol.36 , Issue.4 , pp. 658-665
    • Bhavnaganwala, A.1    Tang, X.2    Meindl, J.D.3
  • 5
    • 19944430414 scopus 로고    scopus 로고
    • The Design, Analysis, and Development of Highly Manufacturable 6T SRAM Bitcells for SoC Applications
    • February
    • R. Venkatraman et al., "The Design, Analysis, and Development of Highly Manufacturable 6T SRAM Bitcells for SoC Applications," IEEE Transactions on Electron Devices, Vol. 52, No. 2, pp. 218-226, February 2005.
    • (2005) IEEE Transactions on Electron Devices , vol.52 , Issue.2 , pp. 218-226
    • Venkatraman, R.1
  • 9
    • 34548842014 scopus 로고    scopus 로고
    • The MOSIS Service
    • The MOSIS Service, http://www.mosis.org/Technical/Designrules/scmos/ scmos-main.html.
  • 10
    • 0025235208 scopus 로고
    • Design and Analysis of a Gracefully Degrading Interleaved Memory System
    • January
    • K. C. Cheung, G. S. Sohi, K. K. Saluja, and D. K. Pradhan, "Design and Analysis of a Gracefully Degrading Interleaved Memory System," IEEE Transactions on Computers, Vol. 39, No. 1, pp. 63-71, January 1990.
    • (1990) IEEE Transactions on Computers , vol.39 , Issue.1 , pp. 63-71
    • Cheung, K.C.1    Sohi, G.S.2    Saluja, K.K.3    Pradhan, D.K.4
  • 11
    • 0034293891 scopus 로고    scopus 로고
    • A Super Cut-off CMOS (SCCMOS) Scheme for 0.5V Supply Voltage with Picoampere Stand-By Current
    • October
    • H. Kawaguchi et al., "A Super Cut-off CMOS (SCCMOS) Scheme for 0.5V Supply Voltage with Picoampere Stand-By Current," IEEE Journal of Solid-State Circuits, Vol. 35, No. 10, pp. 1498-1501, October 2000.
    • (2000) IEEE Journal of Solid-State Circuits , vol.35 , Issue.10 , pp. 1498-1501
    • Kawaguchi, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.