A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 257-260

  Levacq, David ^a   Minakawa, Takuya ^a,b   Takamiya, Makoto ^a   Sakurai, Takayasu ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b CANON INC   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; THRESHOLD VOLTAGE;

90-NM CMOS; ALPHA-POWER LAW; ON CURRENTS; ON-BODY; SPATIAL FREQUENCY ANALYSIS; THRESHOLD VOLTAGE VARIATION; TRANSISTOR ARRAYS;

SPATIAL VARIABLES MEASUREMENT;

EID: 49749123368     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405727     Document Type: Conference Paper

References (11)

1. J. Tschanz et al., "Adaptive body bias for reducing impacts of die-todie and within-die parameter variations on microprocessor frequency and leakage, " ISSCC Dig. Tech. Papers, pp. 422-423, 2002.
2. T. Mizuno, J. Okumtura and A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's, " IEEE Trans. Electron Dev., 41 (11), pp. 2216-2221, 1994.
3. K. Takeuchi, T. Tatsumi and A. Furukawa, "Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation, " IEDM Tech. Dig., pp. 841-844, 1997.
4. H. Masuda, S. Ohkawa, A. Kurokawa and M. Aoki, "Challenge: variability characterization and modeling for 65-to 90-nm processes, " CICC Proc., pp. 593-599, 2005.
5. L.-T. Pang and B. Nikolic, "Impact of layout on 90nm CMOS process parameter fluctuations, " Symp. on VLSI Circuits Dig. Tech. Papers, pp. 84-85, 2006.
6. K. Agarwal et al., "A test structure for characterizing local device mismatches, " Symp. on VLSI Circuits Dig. Tech. Papers, pp. 82-83, 2006.
7. K. Ishibashi et al., "Low-voltage and low-power logic, memory, and analog circuit techniques for SoCs using 90nm technology and beyond, " IEICE Trans. Electron., E89-C(3), pp. 250-262, 2006.
8. A. Keshavarzi et al., "Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage, " Proc. ISLPED, pp. 26-29, 2005.
9. Q. Liu, T. Sakurai, and T. Hiramoto, "Optimum device consideration for standby power reduction scheme using drain induced barrier lowering (DIBL)", Japanese Journal of Applied Physics, Vol. 42, Part 1, No. 4B, pp. 2171-2175, April, 2003.
10. M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, "Matching properties of MOS transistors, " IEEE J. Solid-State Circuits, 24(5), pp. 1433-1439, 1989.
11. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, " IEEE J. Solid-State Circuits, 25(2), pp. 584-594, 1990.