Optimum device consideration for standby power reduction scheme using drain-induced barrier lowering

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 42, Issue 4 B, 2003, Pages 2171-2175

  Liu, Qingyan ^a   Sakurai, Takayasu ^a,b   Hiramoto, Toshiro ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

Drain induced barrier lowering (DIBL); Low power; Metal oxide semiconductor field effect transistor (MOSFET); S factor; Short channel effect (SCE); Subthreshold leakage current; Supply voltage; Threshold voltage fluctuations

Indexed keywords

COMPUTER SIMULATION; LEAKAGE CURRENTS; MOSFET DEVICES; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

DRAIN INDUCED BARRIER LOWERING; LOW POWER; S FACTOR; SHORT CHANNEL EFFECT; STANDBY POWER REDUCTION; SUBTHRESHOLD LEAKAGE CURRENT; SUPPLY VOLTAGE; THRESHOLD VOLTAGE FLUCTUATIONS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0038009868     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.42.2171     Document Type: Article

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