Defects in the interfacial layer of SiO2-HfO2 gate stacks: Depth distribution and indentification

IEEE International Integrated Reliability Workshop Final Report

Volumn , Issue , 2007, Pages 94-98

  Ghobar, O ^a   Bauza, D ^a   Guillaumot, B ^b,c  

^a IMEP LAHC   (France)

^b CEA LETI   (France)

^c STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; HAFNIUM OXIDES; LOGIC GATES; MOSFET DEVICES; SILICON OXIDES;

CHARGE PUMPING; DEPTH DISTRIBUTION; GATE STACKS; INTERFACE TRAP DENSITY; INTERFACE-TRAP DENSITY; INTERFACIAL LAYER; MOSFETS; SI-SIO 2 INTERFACE; STATE OF THE ART; TRAP DEPTH;

SILICA;

EID: 49549118896     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IRWS.2007.4469229     Document Type: Conference Paper

References (21)

1. Srinivasan et al., "Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks", Micro. Reliab., 47, pp. 501-504 (2007),
2. G. Bersuker et al., "The effect of interfacial layer properties on the performance of Hf-based gate stack devices", J. Appl. Phys., 100, pp. 0941081-6 (2006),
3. 2 interlayer at the interface between silicon and high-κ oxides" Micro. Engineering, 72, pp. 299-303 (2004),
4. 2 stacks subjected to static and dynamic stress conditions", Micro. Reliab., 47, pp. 544-547 (2007),
5. O. Ghobar et al., "On the Depth Profiling of the Traps in MOSFET's with High-κ Gate Dielectrics" ECS Transactions, vol. 6, No1, pp. 219-227 (2007),
6. B. Guillaumot et al., "Metal Gate and High-κ Integration for Advanced CMOS Devices", Proceedings of the IEDM Techn. Dig. Conf., pp. 355-358 (2002),
7. 2 Layers" IEEE Electron Dev. Mat. Reliab., 6, pp. 509-515 (2006),
8. G. Groenseneken et al., "A Reliable Approach to Charge Pumping Measurements in MOS Transistors", IEEE Trans. Electron Devices, ED 31, pp. 42-53 (1984),
9. 2 Gate Dielectric on Ultrathin SiON Buffer Layer" IEEE Electron Device Lett., 25, 126-128 (2004),
10. 2 Interface Traps in MOS Transistors Using the Charge Pumping Technique", IEEE Trans. Electron Devices, ED-44, pp. 2262-2266 (1997),
11. 2 interface trap time constant distibution", J. Appl. Phys., 97, pp. 0145021-7 (2005),
12. D. Bauza et al., "Further Advances in the Electrical Characterisation of Silicon Insulator Interface Traps Using Charge Pumping", ECS Transactions, 6, No3, pp. 3-25 (2007).
13. 2 interface in MOS devices", The Electrochemical Society Proceedings, vol. 2005-1, pp. 33-44.
14. 2 deposited by atomic layer deposition", Appl. Phys. Lett., 83, 3984-3986 (2003),
15. S. Stemmer et al., "Application of Metastable Phase Diagrams to Silicate Thin Films for Alternative Gate dielectrics", Jpn. J. Appl. Phys., 42, pp. 3593-3597 (2003),
16. 2", Appl. Phys. Lett., 84, pp. 1492-1494 (2004),
17. 2/Si films", Appl. Phys. Lett., 84, pp.1305-1307 (2004),
18. 2 transistors with polycrystalline silicon and TiN electrodes", Appl. Phys. Lett., 87, pp. 0829031-3 (2005),
19. P. M. Lenahan et al., "Hole traps and trivalent silicon centers in metal/oxide/silicon devices", J. Appl. Phys., 55, pp. 3495-3499 (1984),
20. 2" Proceedings of the IEDM Techn. Dig. Conf., pp.703-706 (1997),
21. D. M. Fleetwood et al., "Evidence That Similar Point Defects Cause 1/f Noise and Radiation-Induced-Hole Trapping in Metal-Oxide-Semiconductor Transitors", Phys. Rev. Lett., 64, pp. 579-582 (1990).