Concepts and implementation of spatial division multiplexing for guaranteed throughput in networks-on-chip

IEEE Transactions on Computers

Volumn 57, Issue 9, 2008, Pages 1182-1195

  Leroy, Anthony ^a   Milojevic, Dragomir ^a   Verkest, Diederik ^b   Robert, Frédéric ^a   Catthoor, Francky ^b  

^a UNIVERSITÉ LIBRE DE BRUXELLES   (Belgium)

^b IMEC   (Belgium)

Author keywords

Network on chip; Spatial division multiplexing

Indexed keywords

ARTS COMPUTING; BIOLOGICAL MATERIALS; ELECTRIC NETWORK TOPOLOGY; ENERGY POLICY; MICROPROCESSOR CHIPS; MULTIPLEXING; SPACE DIVISION MULTIPLE ACCESS; TELECOMMUNICATION; THROUGHPUT; TIME DIVISION MULTIPLEXING; URBAN PLANNING;

AREA OVERHEAD; ARTERIS; CASE STUDIES; DATA MEMORIES; DESIGN ALTERNATIVES; DIFFERENT SIZES; ENERGY CONSUMPTION; GUARANTEED THROUGHPUT; HETEROGENEOUS PLATFORMS; LOW-POWER CONSUMPTION; NETWORK AREA; NETWORK RESOURCES; NETWORK-ON-CHIP; NETWORKS ON CHIPS; NETWORKS-ON-CHIP; PROCESSOR CORES; SET-UP TIME; SHARED BUSES; SPATIAL DIVISION MULTIPLEXING; SYSTEMS-ON-CHIP; VIRTUAL CIRCUITS;

NETWORKS (CIRCUITS);

EID: 49149093493     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2008.82     Document Type: Article

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