Evolution of synthetic RTL benchmark circuits with predefined testability

ACM Transactions on Design Automation of Electronic Systems

Volumn 13, Issue 3, 2008, Pages 1-21

  Pecenka, Tomas ^a   Sekanina, Lukas ^b   Kotasek, Zdenek ^b  

^a ON SEMICONDUCTOR   (United States)

^b BRNO UNIVERSITY OF TECHNOLOGY   (Czech Republic)

Author keywords

Benchmark circuit; Evolvable hardware; Testability analysis

Indexed keywords

DIGITAL CIRCUITS; EVOLUTIONARY ALGORITHMS; TIMING CIRCUITS;

BENCHMARK CIRCUIT; COMPLEX BENCHMARK; EVOLUTIONARY COMPUTING; EVOLVABLE HARDWARE; NOVEL ALGORITHM; SYNTHETIC BENCHMARK; TESTABILITY ANALYSIS; VALIDATION PROCESS;

ELECTRIC NETWORK ANALYSIS;

EID: 48849098494     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1367045.1367063     Document Type: Article

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