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Volumn , Issue , 2007, Pages 940-943

Introducing OperaNP: A reconfigurable NoC-based platform

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; INTELLECTUAL PROPERTY; INTERNET PROTOCOLS; RESEARCH; ROUTERS; SWITCHING CIRCUITS; TOPOLOGY;

EID: 48749104224     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCECE.2007.240     Document Type: Conference Paper
Times cited : (9)

References (13)
  • 1
    • 33745800231 scopus 로고    scopus 로고
    • A survey of research and practices of network-on-chip
    • Mar
    • T. Bjerregaard and K. Mahadevan, "A survey of research and practices of network-on-chip," ACM Computing Surveys, vol. 38, pp. 1-51, Mar. 2006.
    • (2006) ACM Computing Surveys , vol.38 , pp. 1-51
    • Bjerregaard, T.1    Mahadevan, K.2
  • 2
    • 48749123283 scopus 로고    scopus 로고
    • D. Siguenza-Tortosa and J. Nurmi, Proteo: A new approach to network-on-chip, in Proceedings of the International Conference on Communication Systems and Network (IASTED'02), (Malaga, Spain), pp. 371-091, Sept. 9-12, 2002.
    • D. Siguenza-Tortosa and J. Nurmi, "Proteo: A new approach to network-on-chip," in Proceedings of the International Conference on Communication Systems and Network (IASTED'02), (Malaga, Spain), pp. 371-091, Sept. 9-12, 2002.
  • 3
    • 48749120226 scopus 로고    scopus 로고
    • M. Alho and J. Nurmi, Implementation of interface router IP for Proteo Network-on-Chip, (Poznan, Poland), Apr. 14-16, 2003. Proceedings of the 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03).
    • M. Alho and J. Nurmi, "Implementation of interface router IP for Proteo Network-on-Chip," (Poznan, Poland), Apr. 14-16, 2003. Proceedings of the 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03).
  • 6
    • 48749092219 scopus 로고    scopus 로고
    • A user introduction to NNSE: Nostrum Network-on-Chip simulation environment,
    • Royal Institute of Technology, Stockholm, Sweden, Nov
    • Z. Lu, "A user introduction to NNSE: Nostrum Network-on-Chip simulation environment," tech. rep., Royal Institute of Technology, Stockholm, Sweden, Nov. 2005.
    • (2005) tech. rep
    • Lu, Z.1
  • 11
  • 12
    • 0036760592 scopus 로고    scopus 로고
    • An interconnect architecture for networking systems on chips
    • Sept
    • F. Karim, A. Nguyen, and S. Dey, "An interconnect architecture for networking systems on chips," IEEE Micro, vol. 22, pp. 36-45, Sept. 2002.
    • (2002) IEEE Micro , vol.22 , pp. 36-45
    • Karim, F.1    Nguyen, A.2    Dey, S.3
  • 13
    • 24144461667 scopus 로고    scopus 로고
    • Performance evaluation and design trade-offs for network-on-chip interconnect architectures
    • Aug
    • P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Transactions on Computers, vol. 54, pp. 1025-1040, Aug. 2005.
    • (2005) IEEE Transactions on Computers , vol.54 , pp. 1025-1040
    • Pande, P.P.1    Grecu, C.2    Jones, M.3    Ivanov, A.4    Saleh, R.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.