Impact of NBTI on FPGAs

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 717-722

  Ramakrishnan, K ^a   Suresh, S ^a   Vijaykrishnan, N ^a   Irwin, M J ^a   Degalahal, Vijay ^b  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b INTEL TECHNOLOGY INDIA PVT LTD   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPREHENSIVE ANALYSIS; DETRIMENTAL EFFECTS; DEVICE SCALING; DIGITAL SYSTEMS; FIT RATE; HIGH ELECTRIC FIELDS; INTERNATIONAL CONFERENCES; NEGATIVE BIAS- TEMPERATURE-INSTABILITY (NBTI); NOISE DEGRADATIONS; OXIDE THICKNESSES; PMOS DEVICES; SRAM CELLS; STATIC NOISE MARGIN (SNM); VLSI DESIGNS;

CMOS INTEGRATED CIRCUITS; COMPUTER PROGRAMMING LANGUAGES; DEGRADATION; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC FIELDS; ELECTROMAGNETIC FIELD THEORY; ELECTROMAGNETIC FIELDS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; NEGATIVE TEMPERATURE COEFFICIENT; RADIOACTIVE MATERIALS; RISK ASSESSMENT; SULFATE MINERALS; THERMODYNAMIC STABILITY; TIMING CIRCUITS;

EMBEDDED SYSTEMS;

EID: 48349124345     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.91     Document Type: Conference Paper

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