메뉴 건너뛰기




Volumn , Issue , 2007, Pages 18-25

FlexCore: Utilizing exposed datapath control for efficient computing

Author keywords

[No Author keywords available]

Indexed keywords

CODE GENERATIONS; CYCLE COUNTING; DATA PATHS; DATA-PATH UNITS; EMBEDDED APPLICATIONS; EMBEDDED COMPUTER SYSTEMS; ENERGY SAVINGS; FINE-GRAINED CONTROL; GENERAL-PURPOSE PROCESSOR; INTERNATIONAL CONFERENCES; MEMORY FOOTPRINTS; MODELING AND SIMULATION; VLSI IMPLEMENTATION;

EID: 47749104166     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSAMOS.2007.4285729     Document Type: Conference Paper
Times cited : (19)

References (21)
  • 2
    • 33748538011 scopus 로고    scopus 로고
    • Utilizing horizontal and vertical parallelism with no-instruction-set compiler for custom datapaths
    • October
    • M. Reshadi, B. Gorjiara, and D. Gajski, "Utilizing horizontal and vertical parallelism with no-instruction-set compiler for custom datapaths," in International Conference on Computer Design (ICCD), October 2005.
    • (2005) International Conference on Computer Design (ICCD)
    • Reshadi, M.1    Gorjiara, B.2    Gajski, D.3
  • 3
    • 47749106756 scopus 로고    scopus 로고
    • A hardware audio decoder using flexible datapaths,
    • MSc Thesis, Chalmers University of Technology, March
    • J. Mårts and T. Carlqvist, "A hardware audio decoder using flexible datapaths," MSc Thesis, Chalmers University of Technology, March 2006.
    • (2006)
    • Mårts, J.1    Carlqvist, T.2
  • 5
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-way multithreaded sparc processor
    • P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-way multithreaded sparc processor," IEEE Micro, vol. 25, no. 2, pp. 21-29, 2005.
    • (2005) IEEE Micro , vol.25 , Issue.2 , pp. 21-29
    • Kongetira, P.1    Aingaran, K.2    Olukotun, K.3
  • 6
    • 27544432558 scopus 로고    scopus 로고
    • The impact of performance asymmetry in emerging multicore architectures
    • S. Balakrishnan, R. Rajwar, M. Upton, and K. Lai, "The impact of performance asymmetry in emerging multicore architectures," SIGARCH Comput. Archit. News, vol. 33, no. 2, pp. 506-517, 2005.
    • (2005) SIGARCH Comput. Archit. News , vol.33 , Issue.2 , pp. 506-517
    • Balakrishnan, S.1    Rajwar, R.2    Upton, M.3    Lai, K.4
  • 9
    • 47749120944 scopus 로고    scopus 로고
    • Encounter User Guid Version 4.1
    • Encounter User Guid Version 4.1.
  • 13
    • 4644353790 scopus 로고    scopus 로고
    • M. B. T. et al., Evaluation of the RAW microprocessor: An exposed-wire-delay architecture for ILP and streams, in ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture. Washington, DC, USA: IEEE Computer Society, 2004, p. 2.
    • M. B. T. et al., "Evaluation of the RAW microprocessor: An exposed-wire-delay architecture for ILP and streams," in ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture. Washington, DC, USA: IEEE Computer Society, 2004, p. 2.
  • 14
    • 84905483003 scopus 로고    scopus 로고
    • K. S. et al., TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP, ACM Trans. Archit. Code Optim., 1, no. 1, pp. 62-93, 2004.
    • K. S. et al., "TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP," ACM Trans. Archit. Code Optim., vol. 1, no. 1, pp. 62-93, 2004.
  • 16
    • 0039180035 scopus 로고    scopus 로고
    • Ttas: Missing the ilp complexity wall
    • H. Corporaal, "Ttas: missing the ilp complexity wall," J. Syst. Archit., vol. 45, no. 12-13, pp. 949-973, 1999.
    • (1999) J. Syst. Archit , vol.45 , Issue.12-13 , pp. 949-973
    • Corporaal, H.1
  • 17
    • 47749133718 scopus 로고    scopus 로고
    • Dynamic coarse grain dataflow reconfiguration technique for real-time systems design
    • IEEE Computer Society, May
    • X. Liang, A. Athalye, and S. Hong, "Dynamic coarse grain dataflow reconfiguration technique for real-time systems design," in The 2005 IEEE International Symposium on Circuits and Systems. IEEE Computer Society, May 2005, pp. 3511-3514.
    • (2005) The 2005 IEEE International Symposium on Circuits and Systems , pp. 3511-3514
    • Liang, X.1    Athalye, A.2    Hong, S.3
  • 21
    • 33646058284 scopus 로고    scopus 로고
    • High-quality ISA synthesis for low-power cache designs in embedded microprocessors
    • A. C. Cheng and G. S. Tyson, "High-quality ISA synthesis for low-power cache designs in embedded microprocessors," IBM J. Res. Dev., vol. 50, no. 2, pp. 299-309, 2006.
    • (2006) IBM J. Res. Dev , vol.50 , Issue.2 , pp. 299-309
    • Cheng, A.C.1    Tyson, G.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.