FITS: Framework-based instruction-set tuning synthesis for embedded application specific processors

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 920-923

  Cheng, Allen ^a   Tyson, Gary ^b   Mudge, Trevor ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b Florida State University   (United States)

Author keywords

16 bit ISA; ASP; Code density; Configurable architecture; Embedded processor; Energy efficient; Instruction encoding; Instruction synthesis; Low power; Reconfigurable processors

Indexed keywords

16-BIT ISA; CODE DENSITY; CONFIGURABLE ARCHITECTURE; EMBEDED PROCESSOR; INSTRUCTION ENCODING; INSTRUCTION SYNTHESIS; RECONFIGURABLE PROCESSORS;

ALGORITHMS; COMPUTER SOFTWARE; COSTS; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; FREQUENCIES; PERSONAL DIGITAL ASSISTANTS; SIGNAL ENCODING; STORAGE ALLOCATION (COMPUTER);

PROGRAM PROCESSORS;

EID: 4444328472     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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4. C. Lefurgy, E. Piccininni, and T. Mudge, "Reducing Code Size with Run-time Decompression," in Proceedings of 6th International Symposium on High-Performance Computer Architecture (HPCA), Jan. 2000, pp. 218-227.
5. K. D. Kissell, "MIPS 16: High-density MIPS for the Embedded Market," in Proceedings of Real Time Systems, 1997.
6. MiBench Version. 1.0, http://www.eecs.umich.edu/mibench.
7. MIRV Compiler Group, http://www.eecs.umich.edu/mirv.
8. SimpleScalar LLC, http://www.simplescalar.com
9. ST100 Technical Manual, STMicroelectronics, http://www.st.com.