The impact of dynamically heterogeneous multicore processors on thread scheduling

IEEE Micro

Volumn 28, Issue 3, 2008, Pages 17-25

  Bower, Fred A ^a,b   Sorin, Daniel J ^b   Cox, Landon P ^b  

^a IBM   (United States)

^b DUKE UNIVERSITY   (United States)

Author keywords

Heterogeneous; Multicore; Operating system; Power efficiency; Scheduling

Indexed keywords

DYNAMIC HETEROGENEITIES; HETEROGENEOUS MULTICORE; MULTI CORE PROCESSORS; OPERATING SYSTEMS; PERFORMANCE LOSSES; POWER EFFICIENCIES; RUN TIME; THREAD SCHEDULING;

SCHEDULING;

EID: 47249107273     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2008.46     Document Type: Article

References (23)

1. M, Gschwind et al., "Synergistic Processing in Cell's Multicore Architecture," IEEE Micro, vol 26, no 2, Mar.-Apr. 2006, pp. 10-24.
2. P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-way Multithreaded SPARC Processor," IEEE Micro, vol. 25, no. 2, Mar.-Apr. 2005, pp. 21-29.
3. R. Kalla, B. Sinharoy, and J.M. Tendler, "IBM POWER5 Chip: A Dual-Core Multithreaded Processor," IEEE Micro, vol.24, no. 2, Mar.-Apr. 2004, p.p. 40-47.
4. A. Fedorova et al., "Performance of Multithreaded Chip Multiprocessors and Implications for Operating System Design," Proc. Usenix 2005 Ann. Technical. Conf., Usenix Assoc, 2005, p. 26.
5. A. Fedorova, M. Seltzer, and M.D. Smith, "Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler," Proc. Int'l Conf. Parallel Architectures and Compilation Techniques (PACT 07), 2007, pp. 25-38.
6. S. Balakrishnan et al., "The impact of Performance Asymmetry in Emerging Multicore Architecture," Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA 05). IEEE CS Press, 2005, pp. 506-517.
7. R. Kumar et al., "Heterogeneous Chip Multiprocessors," Computer, vol. 38, no. 11, Nov. 2005, pp. 32-38.
8. D.M. Tullsen et al., "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor," Proc. 23rd Ann. Int'l Symp. Computer Architecture (ISCA 96), IEEE CS Press, 1996, pp. 191-202.
9. S. Borkar, "Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation," IEEE Micro vol. 25, no. 6, Nov.-Dec. 2005, p.p. 10-16.
10. J. Srinivasan et al., "The Impact of Technology Scaling on Lifetime Relialibility," Proc. Int'l Conf. Dependable Systems and Networks (DSN 04), IEEE CS Press, 2004, p. 177.
11. J. Blome et al., "Self-Calibrating Online Wearout Detection," Proc. 40th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro 07), IEEE CS Press, 2007, pp. 109-122.
12. D. Lampret, OpenRISC 1200 IP Core Specification, Rev. 0.7 2001 http://www.opencores.org.
13. F.A. Bower, S. Ozev, and D.J. Sorin, "Autonomic Microprocessor Execution via Self-Repairing Arrays," IEEE Trans. Dependable Secure Computing, vol. 2, no. 4, Oct-Dec. 2005, pp. 297-310.
14. F.A. Bower, D.J. Sorin, and S. Ozev, "A Mechanism for Online Diagnosis of Hard Faults in Microprocessors," Proc. 38th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro 05), IEEE CS Press, 2005, pp. 197-208.
15. S Ghiasi, T. Keller, and F. Rawson, "Scheduling for Heterogeneous Processors in Server Systems," Proc. 2nd Conf. Computing Frontiers (CF 05), ACM Press, 2005, pp. 199-210.
16. C. Isci et al., "An Analysis of Efficient Multicore Global Power Management Policies: Maximizing Performance for a Given Power Budget," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro 06), IEEE CS Press, 2006, pp. 347-358.
17. J. Sartori and R. Kumar, Proactive Peak Power Management for Many-Core Architectures, tech. report CRHC-07-04, Center for Reliable and High-Performance Computing, Univ. of Illinois at Urbana-Champaign, 2001.
18. D. Boggs et al., "The Microarchitecture of the Intel Pentium 4 Processor on 90 nm Technology," Intel Tech. J., vol. 8, no. 1, Feb. 2004, pp 1-18.
19. J.C. Dehnert et al., "The Transmeta Code Morphing Software: Using Speculation, Recovery, and Adaptive Retranslation to Address Real-Life Challenges," Proc. Int'l Symp. Code Generation and Optimization (CGO 03), IEEE CS Press, 2003, pp. 115-24.
20. T. Sherwood et al., "Automatically Characterizing Large Scale Program. Behavior," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 45-57.
21. R. Kumar, D.M. Tullsen, and N.P. Jouppi, "Core Architecture Optimization for Heterogeneous Chip Multiprocessors," Proc. Int'l Conf. Parallel Architectures and Compilation Techniques (PACT 06), ACM Press, 2006, pp. 23-32.
22. M. DeVuyst, R. Kumar, and D.M. Tullsen, "Exploitung Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors," Proc. IEEE Int'l Parallel and Distributed Processing Symposium (IPDPS 06), 2006, p. 117.
23. P.M. Wells, K. Chakraborty, and G.S. Sohi, "Adapting to Intermittent Faults in Multicore Systems," Proc. 13th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 08), ACM Press, 2008, pp. 255-264.