-
2
-
-
4444379636
-
Design and implementation of the POWER5 microprocessor
-
J. Clabes, J. Friedrich, M. Sweet, J. DiLullo, S. Chu, D. Plass, J. Dawson, P. Muench, L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz, S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill, and S. Dodson. Design and implementation of the POWER5 microprocessor. In DAC '04: Proceedings of the 41st annual conference on Design automation, pages 670-672, 2004.
-
(2004)
DAC '04: Proceedings of the 41st annual conference on Design automation
, pp. 670-672
-
-
Clabes, J.1
Friedrich, J.2
Sweet, M.3
DiLullo, J.4
Chu, S.5
Plass, D.6
Dawson, J.7
Muench, P.8
Powell, L.9
Floyd, M.10
Sinharoy, B.11
Lee, M.12
Goulet, M.13
Wagoner, J.14
Schwartz, N.15
Runyon, S.16
Gorman, G.17
Restle, P.18
Kalla, R.19
McGill, J.20
Dodson, S.21
more..
-
4
-
-
19644366331
-
Aide de camp: Asymmetric dual core design for power and energy reduction
-
Technical report, University of Colorado, Boulder
-
S. Ghiasi and D. Grunwald. Aide de camp: Asymmetric dual core design for power and energy reduction. Technical report, University of Colorado, Boulder, 2003.
-
(2003)
-
-
Ghiasi, S.1
Grunwald, D.2
-
5
-
-
12344252114
-
Heat-and-run: Leveraging SMT and CMP to manage power density through the operating system
-
M. Gomaa, M. D. Powell, and T. N. Vijaykumar. Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. SIGPLAN Not., 39(11):260-270, 2004.
-
(2004)
SIGPLAN Not
, vol.39
, Issue.11
, pp. 260-270
-
-
Gomaa, M.1
Powell, M.D.2
Vijaykumar, T.N.3
-
6
-
-
84944403811
-
Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction
-
R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan, and D. M. Tullsen. Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction. In MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, 2003.
-
(2003)
MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
-
-
Kumar, R.1
Farkas, K.I.2
Jouppi, N.P.3
Ranganathan, P.4
Tullsen, D.M.5
-
7
-
-
4644370318
-
Single-ISA Heterogeneous Multi-core Architectures for Multithreaded Workload Performance
-
June
-
R. Kumar, D. M. Tullsen, P. Ranganathan, N. P. Jouppi, and K. I. Farkas. Single-ISA Heterogeneous Multi-core Architectures for Multithreaded Workload Performance. In International Symposium on Computer Architecture, June 2004.
-
(2004)
International Symposium on Computer Architecture
-
-
Kumar, R.1
Tullsen, D.M.2
Ranganathan, P.3
Jouppi, N.P.4
Farkas, K.I.5
-
8
-
-
0013229812
-
Thread-sensitive scheduling for SMT processors
-
Technical report, University of Washington, Apr
-
S. Parekh, S. Eggers, and H. Levy. Thread-sensitive scheduling for SMT processors. Technical report, University of Washington, Apr. 2000.
-
(2000)
-
-
Parekh, S.1
Eggers, S.2
Levy, H.3
-
9
-
-
8344233355
-
The energy efficiency of CMP vs. SMT for multimedia workloads
-
R. Sasanka, S. V. Adve, Y.-K. Chen, and E. Debes. The energy efficiency of CMP vs. SMT for multimedia workloads. In ICS '04: Proceedings of the 18th annual International Conference on Supercomputing, pages 196-206, 2004.
-
(2004)
ICS '04: Proceedings of the 18th annual International Conference on Supercomputing
, pp. 196-206
-
-
Sasanka, R.1
Adve, S.V.2
Chen, Y.-K.3
Debes, E.4
-
10
-
-
85008056730
-
The danger of interval-based power efficiency metrics: When worst is best
-
Jan
-
Y. Sazeides, R. Kumar, D. M. Tullsen, and T. Constantinou. The danger of interval-based power efficiency metrics: When worst is best. In Computer Architecture Letters, Vol 4, Jan. 2005.
-
(2005)
Computer Architecture Letters
, vol.4
-
-
Sazeides, Y.1
Kumar, R.2
Tullsen, D.M.3
Constantinou, T.4
-
12
-
-
10444263677
-
Architectural support tor enhanced SMT job scheduling
-
A. Settle, J. L. Kihm, A. Janiszewski, and D. A. Connors. Architectural support tor enhanced SMT job scheduling. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 63-73, 2004.
-
(2004)
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT)
, pp. 63-73
-
-
Settle, A.1
Kihm, J.L.2
Janiszewski, A.3
Connors, D.A.4
-
20
-
-
0029666641
-
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
-
May
-
D. Tullsen, S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In 23rd Annual International Symposium on Computer Architecture, May 1996.
-
(1996)
23rd Annual International Symposium on Computer Architecture
-
-
Tullsen, D.1
Eggers, S.2
Emer, J.3
Levy, H.4
Lo, J.5
Stamm, R.6
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