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Volumn , Issue , 2007, Pages 577-583

Functions and architectures for LDPC decoding

Author keywords

[No Author keywords available]

Indexed keywords

CYBERNETICS; DECODING; INFORMATION THEORY;

EID: 46749145386     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITW.2007.4313138     Document Type: Conference Paper
Times cited : (8)

References (19)
  • 2
    • 0036504121 scopus 로고    scopus 로고
    • A 690mw 1Gb/s, rate-1/2 low-density parity-check code decoder
    • Mar
    • A. Blanksby and C. Howland, "A 690mw 1Gb/s, rate-1/2 low-density parity-check code decoder," IEEE Journal of Solid-State Circuits, vol. 37, pp. 404-412, Mar. 2002.
    • (2002) IEEE Journal of Solid-State Circuits , vol.37 , pp. 404-412
    • Blanksby, A.1    Howland, C.2
  • 3
    • 0035294983 scopus 로고    scopus 로고
    • VLSI architectures for iterative decoders in magnetic recording channels
    • Mar
    • E. Yeo, P. Pakzad, B. Nikolic and V. Anantharam, "VLSI architectures for iterative decoders in magnetic recording channels," IEEE Trans. Magnetics, vol. 37, pp. 784-755, Mar. 2001.
    • (2001) IEEE Trans. Magnetics , vol.37 , pp. 784-755
    • Yeo, E.1    Pakzad, P.2    Nikolic, B.3    Anantharam, V.4
  • 5
    • 5044251189 scopus 로고    scopus 로고
    • Methods and apparatus for decoding LDPC codes,
    • United States Patent 6,633,856, Oct. 14
    • T. Richardson and R. Urbanke, "Methods and apparatus for decoding LDPC codes," United States Patent 6,633,856, Oct. 14, 2003.
    • (2003)
    • Richardson, T.1    Urbanke, R.2
  • 7
    • 0842289304 scopus 로고    scopus 로고
    • Decoder architecture for array-code-based LDPC codes
    • Dec
    • S. Olcer, "Decoder architecture for array-code-based LDPC codes." IEEE Global Telecommunications Conference, vol. 4, pp. 2046-2050, Dec. 2003.
    • (2003) IEEE Global Telecommunications Conference , vol.4 , pp. 2046-2050
    • Olcer, S.1
  • 8
    • 15544377481 scopus 로고    scopus 로고
    • Generic architecture for LDPC codes decoding,
    • Ph.D. dissertation, Telecom Paris
    • F. Guilloud, "Generic architecture for LDPC codes decoding," Ph.D. dissertation, Telecom Paris, 2004.
    • (2004)
    • Guilloud, F.1
  • 10
    • 33847717410 scopus 로고    scopus 로고
    • A 170Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA
    • 21-24 May
    • Z. Wang and Q. Jia, "A 170Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA," The 2006 IEEE International Symposium on Circuits and Systems, 21-24 May 2006, pp. 5095-5098.
    • (2006) The 2006 IEEE International Symposium on Circuits and Systems , pp. 5095-5098
    • Wang, Z.1    Jia, Q.2
  • 13
    • 0035138658 scopus 로고    scopus 로고
    • A reduced-complexity decoding algorithm for low-density parity-check codes
    • Jan
    • E. Eleftheriou, T. Mittelholzer, and A. Dholakia,"A reduced-complexity decoding algorithm for low-density parity-check codes", IEE Electron. Letters, vol. 37, pp. 102-104, Jan. 2001.
    • (2001) IEE Electron. Letters , vol.37 , pp. 102-104
    • Eleftheriou, E.1    Mittelholzer, T.2    Dholakia, A.3
  • 15
  • 17
    • 0033099611 scopus 로고    scopus 로고
    • Good error-correcting codes based on very sparse matrices
    • Mar
    • D. J. C. MacKay, "Good error-correcting codes based on very sparse matrices", IEEE Trans. Inf. Theory, vol. 45, no. 3, pp. 399-431, Mar. 1999.
    • (1999) IEEE Trans. Inf. Theory , vol.45 , Issue.3 , pp. 399-431
    • MacKay, D.J.C.1
  • 18
    • 33846590419 scopus 로고    scopus 로고
    • Low Density Parity Check (LDPC) Codes Constructed from Protographs
    • 42-154, Aug. 2003
    • J. Thorpe,"Low Density Parity Check (LDPC) Codes Constructed from Protographs", JPL INP Progress Report 42-154, Aug. 2003.
    • JPL INP Progress Report
    • Thorpe, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.