A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 5095-5098

  Cui, Zhiqiang ^a   Wang, Zhongfeng ^a  

^a Oregon State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER HARDWARE; DECODING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); ITERATIVE METHODS; MESSAGE PASSING; OPTIMIZATION;

DECODER ARCHITECTURE; PARALLEL DECODING ARCHITECTURE; SOFT MESSAGE MEMORIES;

VLSI CIRCUITS;

EID: 33847717410     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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