Event-driven modeling and simulation of an digital PLL

BMAS 2006 - Proceedings of the 2006 IEEE International Behavioral Modeling and Simulation Workshop

Volumn , Issue , 2006, Pages 67-72

  Zhuang, Jingcheng ^a   Du, Qingjin ^a   Kwasniewski, Tad ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MATLAB; PHASE NOISE; TIME DOMAIN ANALYSIS;

BEHAVIORAL MODELING; EVENT-DRIVEN MODELING; MATHEMATICAL MANIPULATION;

PHASE LOCKED LOOPS;

EID: 43549083066     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BMAS.2006.283472     Document Type: Conference Paper

References (6)

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3. J.Lin.B. Haroun,:T. Foo, Jin-Sheng Wang,B. Helmick, S. Randall, T. Mayhugh, C. Barr, J. Kirkpatric, "A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS, process", Digest of Technical Papers. IEEE International Solid-State Circuits Conference 2004, Pages: 488-541 Vol.1.
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5. A. M.Fahim, "A compact, low-power low-jitter digital PLL", Proceedings of the 29th European Solid-State Circuits Conference, Pages: 101-104.
6. R. B. Staszewski, C. Fernando, P. T. Balsara, "Event-driven Simulation and modeling of phase noise of an RF oscillator", IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 52, Issue 4, April 2005, Pages; 723-733.