Time Behavioral Model for Phase-Domain ADPLL based frequency synthesizer

Proceedings - 2006 IEEE Radio and Wireless Symposium

Volumn 2006, Issue , 2006, Pages 167-170

  Joubert, Cyril ^a,b   Bercher, Jean François ^a   Baudoin, Geneviève ^a   Divel, Thierry ^b   Ramet, Serge ^b   Level, Philippe ^b  

^a ESIEE PARIS   (France)

^b STMICROELECTRONICS   (France)

Author keywords

Modeling; Phase locked loops

Indexed keywords

COMPUTER SIMULATION; FREQUENCY MODULATION; MATHEMATICAL MODELS; PERTURBATION TECHNIQUES; TIME SERIES ANALYSIS;

BASEBAND ANALYSIS; POWER SPECTRAL DENSITY; STEADY STATES; TRANSIENT RESPONSES;

PHASE LOCKED LOOPS;

EID: 33846382373     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. R. B. Staszeswski and P. T. Balsara, "Phase-Domain All-Digital Phase-Locked Loop," IEEE trans. on circuits and System, vol. 52, no. 3, pp. 353-163, March 2005.
2. R. B. Staszewski, C-M. Hung, D. Leipold and P. T. Balsara, "A first Multigigahertz Digitally Controlled Oscillator for Wireless Applications," IEEE Trans. on Microwave Theory and Techniques, vol. 51, no. 11, pp. 2154-2164, Nov 2003.
3. R. B. Staszewski, D. Leipold, C-M. Hung and P. T. Balsara, "TDC-Based Frequency Synthesizer for Wireless Applications," IEEE RFIC Symposium, pp. 215-218, 2004.