RAPID: Reconfigurable and scalable all-photonic interconnect for distributed shared memory multiprocessors

Journal of Lightwave Technology

Volumn 22, Issue 9, 2004, Pages 2101-2110

  Kodi, Avinash Karanth ^a   Louri, Ahmed ^a  

^a University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; COMPUTER SIMULATION; FIBER OPTIC NETWORKS; MULTIPROCESSING SYSTEMS; OPTICAL COMMUNICATION; OPTICAL DATA STORAGE; TELECOMMUNICATION TRAFFIC; TIME DIVISION MULTIPLEXING; WAVELENGTH DIVISION MULTIPLEXING;

CACHE COHERENCE; DISTRIBUTED SHARED MEMORY; OPTICAL COMPONENTS; REMOTE MEORY ACCESS; SCALABLE OPTICAL NETWORKS; SPACE DIVISION MULTIPLEXING;

OPTICAL INTERCONNECTS;

EID: 4644280258     PISSN: 07338724     EISSN: None     Source Type: Journal    
DOI: 10.1109/JLT.2004.833249     Document Type: Article

References (28)

1. D. E. Culler, J. P. Singh, and A. Gupta, Parallel Computer Architecture: A Hardware/Software Approach. San Fransisco, CA: Morgan Kaufmann, 1999.
2. D. E. Lenoski and W.-D. Weber, Scalable Shared-Memory Multiprocessing. San Fransisco, CA: Morgan Kaufmann, 1995.
3. J. Laudon and D. Lenoski, "SGI origin: A ccNUMA highly scalable server," in Proc. 24th Annual Int. Symp. Computer Architecture, June 1997, pp. 241-251.
4. K. Gharachorloo, D. Lenoski, J. Laudon, P. Gibbons, A. Gupta, and J. Hennessy, "Memory consistency and event ordering in scalable shared-memory multiprocessors," in Proc. 17th Ann. Int. Symp. Computer Architecture, May 1990, pp. 15-26.
5. D. Dai and D. K. Panda, "How much does network contention affect distributed shared memory performance," in Int. Conf. Parallel Processing (ICPP '97), 1997, pp. 454-461.
6. D. Dai, "How can we design better networks for DSM systems?," Lecture Notes in Comp. Sci., vol. 1417, pp. 171-184, 1998.
7. S. P. Dandamudi, "Reducing hot-spot contention in shared-memory multiprocessors," IEEE Concurrency, vol. 7, pp. 48-59, 1999.
8. D. A. B. Miller, "Rationale and challenges for optical interconnects to electronic chips," Proc. IEEE, vol. 88, pp. 728-749, June 2000.
9. J. H. Collet, D. Litaize, J. V. Campenhut, C. Jesshope, M. Desmulliez, H. Thienpont, J. Goodman, and A. Loud, "Architectural approaches to the role of optics in mono and multiprocessor machines," Appl. Opt., Special Issue on Optics in Computing, vol. 39, pp. 671-682, 2000.
10. R. Pu, E. M. Hayes, C. W. Wilmsen, K. D. Ohoquette, H. Q. Hou, and K. M. Geib, "Comparison of techniques for bonding VCSEL' s directly to ICs" J. Opt. Soc. Amer., vol. 1, pp. 324-329, 1999.
11. H. J. J. Yeh and J. S. Smith, "Integration of GaAs vertical cavity surface emitting laser on Si by substrate removal," Appl. Phys. Lett., vol. 64, pp. 1466-1468, 1994.
12. M. Arai, T. Kondo, A. Matsutani, T. Miyamoto, and F. Koyama, "Growth of highly strained GaInAs-GaAs quantum wells on patterned substrate and its application for multiple-wavelength vertical-cavity surface-emitting laser array," IEEE J. Select. Topics Quantum Electron., vol. 8, pp. 811-816, July/Aug. 2002.
13. M. K. Smit and C. Van Dam, "PHASAR-based WDM-devices: Principles, design and applications," IEEE J. Select. Topics Quantum Electron., vol. 2, pp. 236-250, June 1996.
14. H. Takahashi, S. Suzuki, and I. Nishi, "Wavelength multiplexer based on SiO2-Ta2O5 arrayed-waveguide grating," J. Lightwave Technol., vol. 12, pp. 989-995, June 1994.
15. R. Ramaswami and K. Sivarajan, Optical Networks: A Practical Perspective. San Fransisco, CA: Morgan Kaufmann, 2001.
16. A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, "16 × 16 VCSEL array flip-chip bonded to CMOS VLSI circuit," IEEE Photon. Technol. Lett., vol. 12, pp. 1073-1075, Aug. 2000.
17. Y. Liu, "Heterogeneous integration of OE arrays with Si electronics and micro-optics," in Proc. Electron. Comp. Technol. Conf., 2001, pp. 864-869.
18. J.-H. Ha and T. M. Pinkston, "The speed cache coherence for an optical multi-access interconnect architecture," in Proc. 2nd Int. Conf. Massively Parallel Processing Using Optical Interconnections, 1995, pp. 98-107.
19. P. Dowd, J. Perreault, J. Chu, D. C. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y. J. Chen, and M. Dagenais, "Lightning network and systems architecture," J. Lightwave Technol., vol. 14, pp. 1371-1387, 1996.
20. K. Bogineni and P. W. Dowd, "A collisionless multiple access protocol for wavelength division multiplexed star-coupled configuration: Architecture and performance analysis," J. Lightwave Technol., vol. 10, pp. 1688-1699, 1992.
21. A. Kodi and A. Louri, "A scalable architecture for distributed shared memory multiprocessors using optical interconnects," in Proc. 18th Int. Parallel Distributed Processing Symp. (IPDPS'04), Sante Fe, NM, Apr. 2004, pp. 11-20.
22. R. R. Patel, S. W. Bond, M. D. Pocha, M. C. Larson, H. E. Garrett, F. Drayton, H. E. Petersen, D. M. Krol, R. J. Deft, and M. E. Lowry, "Multiwavelength parallel optical interconnects for massively parallel processing," IEEE J. Select. Topics Quantum Electron., vol. 9, pp. 657-666, Mar./Apr. 2003.
23. L. Eldada and L. W. Shacklette, "Advances in polymer integrated optics," IEEE J. Select. Topics Quantum Electron., vol. 6, pp. 54-68, 2000.
24. B. Webb and A. Louri, "A class of highly scalable optical crossbar-connected interconnection networks (SOCN's) for parallel computing systems," IEEE Trans. Parallel Distrib. Syst., vol. 11, no. 1, pp. 444-458, May 2000.
25. Y. Hibino, "An array of photonic filtering advantages: Arrayed waveguide-grating multi/demultiplexers for photonic networks;" IEEE LEOS Newslett., Aug. 2001.
26. T. V. Moui, "Receiver design for high-speed optical fiber systems," J. Lightwave Technol., vol. LT-2, pp. 234-267, 1984.
27. H. Schwetman, "CSIM19: a powerful tool for building system models," in Proc. 2001 Winter Simulation Conf., 2001, pp. 250-255.
28. M. E. Acacio, J. Gonzalez, J. M. Garcia, and J. Duato, "The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors," in Proc. Int. Conf. Parallel Architectures and Compilation Techniques, 2002, pp. 155-164.