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1
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0000195442
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Computer-Aided Design Of Analog And Mixed-Signal Integrated Circuits
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December
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G. Gielen, R. Rutenbar, "Computer-Aided Design Of Analog And Mixed-Signal Integrated Circuits," Proceedings of the IEEE, Vol. 88, No. 12, pp. 1825-1854, December 2000.
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(2000)
Proceedings of the IEEE
, vol.88
, Issue.12
, pp. 1825-1854
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Gielen, G.1
Rutenbar, R.2
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2
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27944489940
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R. A. Rutenbar, G. G. E. Gielen, B. Antao, eds, Wiley-IEEE Press, April
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R. A. Rutenbar, G. G. E. Gielen, B. Antao, eds., Computer-Aided Design of Analog Integrated Circuits and Systems, Wiley-IEEE Press, April 2002.
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(2002)
Computer-Aided Design of Analog Integrated Circuits and Systems
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3
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48949106187
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Hierarchical Modeling, Optimization and Synthesis for System-Level Analog and RF Designs
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to appear
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J. Roychowdhury, G.Gielen, R.A. Rutenbar, "Hierarchical Modeling, Optimization and Synthesis for System-Level Analog and RF Designs," Proceedings of the IEEE, to appear, 2007.
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(2007)
Proceedings of the IEEE
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Roychowdhury, J.1
Gielen, G.2
Rutenbar, R.A.3
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5
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0033712180
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A Case Study of Synthesis for Industrial-Scale Analog IP: Redesign of the Equalizer/Filter Frontend for an ADSL CODEC
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June
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R. Phelps, M. Krasnicki, R. A. Rutenbar, L. R. Carley, "A Case Study of Synthesis for Industrial-Scale Analog IP: Redesign of the Equalizer/Filter Frontend for an ADSL CODEC", Proc. ACM/IEEE DAC, June 2000.
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(2000)
Proc. ACM/IEEE DAC
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Phelps, R.1
Krasnicki, M.2
Rutenbar, R.A.3
Carley, L.R.4
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6
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0003591549
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285 pp, Kluwer Academic Publishers, Boston, MA, ISBN: 0-7923-9431-3
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J.M. Conn, D.J. Garrod, R.A. Rutenbar and L.R. Carley, Analog Device-Level Layout Automation, 285 pp., Kluwer Academic Publishers, Boston, MA, 1994. ISBN: 0-7923-9431-3.
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(1994)
Analog Device-Level Layout Automation
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Conn, J.M.1
Garrod, D.J.2
Rutenbar, R.A.3
Carley, L.R.4
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7
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46149096164
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A.H. Shah, Neolinear, S Dugalleix and F Lemery, High-Performance CMOS-Amplifier Design Uses Front-To-Back Analog Flow, EDN, 10/31/2002.
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A.H. Shah, Neolinear, S Dugalleix and F Lemery, "High-Performance CMOS-Amplifier Design Uses Front-To-Back Analog Flow," EDN, 10/31/2002.
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8
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10444274728
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An Automated Approach For Sizing Complex Analog Circuits In A Simulation-Based Flow
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March
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E Hennig, R. Sommer, L. Charlack, " An Automated Approach For Sizing Complex Analog Circuits In A Simulation-Based Flow," Proc. Design Automation and Test, Europe (DATE), March 2002.
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(2002)
Proc. Design Automation and Test, Europe (DATE)
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Hennig, E.1
Sommer, R.2
Charlack, L.3
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9
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84884217201
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A New Methodology for Analog/Mixed-Signal (AMS) SoC Design that Enables AMS Design Reuse and Achieves Full-Custom Performance
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April
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K. Oda, L. Prado, and A. J. Gadient, "A New Methodology for Analog/Mixed-Signal (AMS) SoC Design that Enables AMS Design Reuse and Achieves Full-Custom Performance", Proc. ACM/IEEE Electronic Design Processes Workshop (EDP), April 2002.
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(2002)
Proc. ACM/IEEE Electronic Design Processes Workshop (EDP)
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Oda, K.1
Prado, L.2
Gadient, A.J.3
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10
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46149083910
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Silicon Integration Initiative Si2
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Silicon Integration Initiative (Si2), www.si2.org.
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11
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60449101115
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Design Of Pipeline Analog-To-Digital Converters Via Geometric Programming
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Nov
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M. Hershenson, "Design Of Pipeline Analog-To-Digital Converters Via Geometric Programming", Proc. ACM/IEEE ICCAD, Nov. 2002.
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(2002)
Proc. ACM/IEEE ICCAD
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Hershenson, M.1
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12
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33646933535
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Y.-T. Chien, D. Chen, J.-H. Lou, G.-K. Ma, R. A. Rutenbar, and T. Mukherjee, Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters, in Design Automation and Test in Europe (DATE 2005), March 2005, pp. 279-280.
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Y.-T. Chien, D. Chen, J.-H. Lou, G.-K. Ma, R. A. Rutenbar, and T. Mukherjee, "Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters," in Design Automation and Test in Europe (DATE 2005), March 2005, pp. 279-280.
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13
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33745479802
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SPEED: Synthesis of High-Performance Large Scale Analog/Mixed Signal Circuit
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April 27-29, Hsinchu, Taiwan
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Y.-T. Chien, L.-R. Huang, W.-T. Chen, G.-K. Ma, and T. Mukherjee, "SPEED: Synthesis of High-Performance Large Scale Analog/Mixed Signal Circuit," in IEEE Int'l Symp. on Technology, System and Applications, Design, Automation and Test (VLSI-TSA-DAT '05), April 27-29, 2005, Hsinchu, Taiwan.
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(2005)
IEEE Int'l Symp. on Technology, System and Applications, Design, Automation and Test (VLSI-TSA-DAT '05)
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Chien, Y.-T.1
Huang, L.-R.2
Chen, W.-T.3
Ma, G.-K.4
Mukherjee, T.5
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14
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34547172863
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A CPPLL Hierarchical Optimization Methodology Considering Jitter, Power And Locking Time
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July
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J. Zou, D. Mueller, H. Graeb, U. Schlichtmann, "A CPPLL Hierarchical Optimization Methodology Considering Jitter, Power And Locking Time," Proc. ACM/IEEE DAC, July 2006, pp. 19-24.
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(2006)
Proc. ACM/IEEE DAC
, pp. 19-24
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Zou, J.1
Mueller, D.2
Graeb, H.3
Schlichtmann, U.4
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15
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27944461897
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Performance Space Modeling For Hierarchical Synthesis Of Analog Integrated Circuits
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June
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G..G.E. Gielen, T. McConaghy, T. Eeckelaert, "Performance Space Modeling For Hierarchical Synthesis Of Analog Integrated Circuits," Proc. ACM/IEEE DAC, June 2005, pp. 881-886.
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(2005)
Proc. ACM/IEEE DAC
, pp. 881-886
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Gielen, G.G.E.1
McConaghy, T.2
Eeckelaert, T.3
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16
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34547327558
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Generation Of Yield-Aware Pareto Surfaces For Hierarchical Circuit Design Space Exploration
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July
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S. K. Tiwary, P. K. Tiwary, R. A. Rutenbar, "Generation Of Yield-Aware Pareto Surfaces For Hierarchical Circuit Design Space Exploration," Proc. ACM/IEEE DAC, July 2006, pp. 31 - 36.
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(2006)
Proc. ACM/IEEE DAC
, pp. 31-36
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Tiwary, S.K.1
Tiwary, P.K.2
Rutenbar, R.A.3
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18
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16244368763
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Robust Analog/RF Circuit Design With Projection-Based Posynomial Modeling
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X. Li, P. Gopalakrishnan, Y. Xu and L. Pileggi, "Robust Analog/RF Circuit Design With Projection-Based Posynomial Modeling," Proc. ACM/IEEE ICCAD, pp. 855-862, 2004.
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(2004)
Proc. ACM/IEEE ICCAD
, pp. 855-862
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Li, X.1
Gopalakrishnan, P.2
Xu, Y.3
Pileggi, L.4
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