Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Volumn , Issue , 2004, Pages 127-132

  Celinski, Peter ^a   Al Sarawi, Said ^a   Abbott, Derek ^a   Cotofana, Sorin ^b   Vassiliadis, Stamatis ^b  

^a UNIVERSITY OF ADELAIDE   (Australia)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE RECYCLING; DESIGN EXPLORATION; LOGGING EFFORT (LE);

COMPUTATIONAL METHODS; DELAY CIRCUITS; FORMAL LOGIC; LOGIC GATES; THRESHOLD ELEMENTS; VLSI CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 4544347141     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2004.1339519     Document Type: Conference Paper

References (12)

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