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Volumn 2, Issue , 2002, Pages 657-660

A low-power threshold logic family

Author keywords

[No Author keywords available]

Indexed keywords

DISSIPATED POWER; LOGIC FAMILIES; LOW POWER; RE-PROGRAMMABILITY; RUNTIMES; SELF LOCKS; SIMULATED RESULTS; WORST CASE;

EID: 0038788466     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046254     Document Type: Conference Paper
Times cited : (19)

References (11)
  • 2
    • 0032208465 scopus 로고    scopus 로고
    • ĽPeriodic symmetric functions, serial addition and multiplication with neural networksî
    • S. Cotofana, S. Vassiliadis, ľPeriodic Symmetric Functions, Serial Addition and Multiplication with Neural Networksî, IEEE Trans, on Neural Networks, Vol.9, no.6, pp. 1118-1128, 1998;
    • (1998) IEEE Trans, on Neural Networks , vol.9 , Issue.6 , pp. 1118-1128
    • Cotofana, S.1    Vassiliadis, S.2
  • 5
    • 0026818082 scopus 로고
    • ÌBit-sliced median Ýlter design based on majority gateî
    • C. L. Lee, C.-W. Jen, ìBit-sliced median Ýlter design based on majority gateî, IEE Proceedings- G, Vol.139, no.1, pp. 63-71, 1992;
    • (1992) IEE Proceedings- G , vol.139 , Issue.1 , pp. 63-71
    • Lee, C.L.1    Jen, C.-W.2
  • 7
    • 0030216125 scopus 로고    scopus 로고
    • ÌA compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gatesî
    • Y. Leblebici, H. Ozdemir, A. Kepkep, and U. Cilingiroglu, ìA compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gatesî, IEEE Journal of Solid- State Circuits, Vol.31, no.8, pp. 1141-1150, 1996;
    • (1996) IEEE Journal of Solid- State Circuits , vol.31 , Issue.8 , pp. 1141-1150
    • Leblebici, Y.1    Ozdemir, H.2    Kepkep, A.3    Cilingiroglu, U.4
  • 9
    • 0025503656 scopus 로고
    • Neural computing of arithmetic functionsî
    • K. Y. Siu, J. Bruck, ìNeural Computing of Arithmetic Functionsî, Proc. IEEE, Vol.17, no.10, pp. 1669-1675, 1990;
    • (1990) Proc. IEEE , vol.17 , Issue.10 , pp. 1669-1675
    • Siu, K.Y.1    Bruck, J.2
  • 10
    • 27944492851 scopus 로고
    • ÌA functional MOS transistor featuring gate-level weighted sum and threshold operationsî
    • T. Shibata, T. Ohmi, ìA functional MOS transistor featuring gate-level weighted sum and threshold operationsî, IEEE Transactions on Electron Devices, Vol.39, no.6, pp. 1444-1455, 1992;
    • (1992) IEEE Transactions on Electron Devices , vol.39 , Issue.6 , pp. 1444-1455
    • Shibata, T.1    Ohmi, T.2
  • 11
    • 0030192342 scopus 로고    scopus 로고
    • ÌDifferential current switch logic: A low power DCVS logic familyî
    • D. Somasekhar, K. Roy, ìDifferential current switch logic: a low power DCVS logic familyî, IEEE Journal of Solid-State Circuits, Vol.31, no.7, pp. 981-991, 1996.
    • (1996) IEEE Journal of Solid-State Circuits , vol.31 , Issue.7 , pp. 981-991
    • Somasekhar, D.1    Roy, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.