Energy-delay estimation technique for high-performance microprocessor VLSI adders

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2003, Pages 272-279

  Oklobdzija, Vojin G ^a   Zeydel, Bart R ^a   Dao, Hoang ^a   Mathew, Sanu ^b   Krishnamurthy, Ram ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; ESTIMATION; MICROPROCESSOR CHIPS;

ENERGY-DELAY ESTIMATION;

VLSI CIRCUITS;

EID: 0043136302     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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