Application of logical effort techniques for speed optimization and analysis of representative adders

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2001, Pages 1666-1669

  Dao, Hoang ^a   Oklobdzija, Vojin G ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC INVERTERS; ESTIMATION; GATES (TRANSISTOR); OPTIMIZATION;

DYNAMIC CARRY-LOOKAHEAD ADDER; DYNAMIC KOGGE-STONE ADDER; LOGICAL EFFORT TECHNIQUE; STATIC CARRY-SELECT ADDER; TRANSISTOR-LEVEL ANALYSIS; WIRING CAPACITANCE;

ADDERS;

EID: 0035573195     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Logical effort: Designing fast CMOS circuits
2. Multiplexer-based adder for media signal processing
3. 470ps 64-bit parallel binary adder
4. A sub-nanosecond 0.5μm 64b adder design
5. A logic for high-speed addition
6. Improved CLA scheme with optimized delay
7. Application of logical effort on design of arithmetic blocks in VLSI CMOS Technology