Area efficient, high speed parallel counter circuits using charge recycling threshold logic

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Celinski, Peter ^a   Abbott, Derek ^a   Cotofana, Sorin D ^b  

^a UNIVERSITY OF ADELAIDE   (Australia)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CAPACITORS; VLSI CIRCUITS;

CHARGE RECYCLING THRESHOLD LOGIC;

DIGITAL CIRCUITS;

EID: 0038758737     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. K. Kotani, T. Shibata, M. Imai, and T. Ohmi, "Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment," in ISSCC Digest of Technical Papers, 1995, pp. 320-321.
2. H. Özdemir, A. Kepkep, B. Pamir, Y. Leblebici, and U. Çiliniroǧlu, "A capacitive threshold-logic gate," IEEE JSSC, vol. 31, no. 8, pp. 1141-1149, August 1996.
3. P. Celinski, J. F. López, S. Al-Sarawi, and D. Abbott, "Low power, high speed, charge recycling CMOS threshold logic gate," IEE Electronics Letters, vol. 37, no. 17, pp, 1067-1069, August 2001.
4. M. Padure, S.D. Cotofana, and S. Vassiliadis, "A low-power threshold logic family," in Proc. IEEE International Conference on Electronics, Circuits and Systems, 2002, pp. 657-660.
5. Y. Leblebici, H. Özdemir, A. Kepkep, and U. Çiliniroǧlu, "A compact high-speed (31-5) parallel counter circuit based on capacitive threshold-logic gates," IEEE JSSC, vol. 31, no. 8, pp. 1177-1183, August 1996.
6. M. Padure, S. Coofana, and S. Vassiliadis, "High-speed hybrid Threshold-Boolean logic counters and compressors," in Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems, 2002, pp. 457-460.
7. P. Celinski, J. F. López, S. Al-Sarawi, and D. Abbott, "Low depth carry lookahead addition using charge recycling threshold logic," in Proc. IEEE International Symposium on Circuits and Systems, Phoenix, May 2002, pp. 469-472.
8. L. Dadda, "Some schemes for parallel multipliers," Alta Freq., vol. 34, pp. 349-355, May 1965.
9. S. Muroga, Threshold Logic and Its Applications, Wiley, New York, 1971.
10. W. H. Kautz, "The realization of symmetric switching functions with linear input logical elements," IRE Transactions on Electronic Computers, vol. EC-10, pp. 371-378, March 1961.
11. R. C. Minnick, "Linear-Input Logic," IRE Transactions on Electronic Computers, vol. EC-10, pp. 6-16, March 1961.
12. I. Koren, Computer Arithmetic Algorithms, A. K. Peters, Natick, MA, 2002.
13. E. Rodriguez-Villegas, M.J. Avedillo, J.M. Quintana, G. Huertas, and A. Rueda, "A νMOS based sorter for arithmetic applications," VLSI Design, vol. 11, no. 2, pp. 129-136, 2000.