A 4GHz 130nm address generation unit with 32-bit sparse-tree adder core

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 126-127

  Mathew, Sanu ^a   Anders, Mark ^a   Krishnamurthy, Ram ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; LOGIC DESIGN; LOGIC GATES; OPTIMIZATION; PHASE SHIFTERS; TIMING CIRCUITS; TRANSISTORS;

ADDRESS GENERATION UNIT; CARRY-MERGE LOGIC; KOGGE-STONE ADDER; SINGLE RAIL DYNAMIC LOGIC; SPARSE TREE ADDER CORE;

ADDERS;

EID: 0242443395     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. P. Kogge et al, IEEE Trans. Comp., vol. c22, pp 786-793, Aug. '73.
2. J. Park et al, 2000 VLSI Circuits Symp., pp 192-193.
3. S. Tyagi et al, 2000 IEDM Tech. Digest, pp. 567-570.
4. J. Davis et al, Proc. IEEE, v. 89, pp350-324, Mar '01
5. T. Ghani et al, 2000 VLSI Tech. Symp., pp 174-175.