A novel SET/MOSFET hybrid static memory cell design

IEEE Transactions on Nanotechnology

Volumn 3, Issue 3, 2004, Pages 377-382

  Lee, Bong Hoon ^a   Jeong, Yoon Ha ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

Single electron transistor (SET); SPICE; Static random access memory (SRAM)

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COULOMB BLOCKADE; ELECTRIC POTENTIAL; ELECTRON TUNNELING; MONTE CARLO METHODS; STATIC RANDOM ACCESS STORAGE; TUNNEL JUNCTIONS;

NEGATIVE DIFFERENTIAL CIRCUITS (NDC); SINGLE ELECTRON TRANSISTORS (SET); STATIC MEMORY CELLS; TUNNELING RESISTANCE;

MOSFET DEVICES;

EID: 4544323747     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2004.828581     Document Type: Article

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