Compact model for short channel symmetric doped double-gate MOSFETs

Solid-State Electronics

Volumn 52, Issue 7, 2008, Pages 1064-1070

  Cerdeira, Antonio ^a   Iñiguez, Benjamín ^b   Estrada, Magali ^a  

^a DEPARTAMENTO DE FÍSICA   (Mexico)

^b UNIVERSITAT ROVIRA I VIRGILI   (Spain)

Author keywords

Compact modeling; Doped double gate MOSFET; Double gate current modeling; Short channel effects

Indexed keywords

DOPING (ADDITIVES); ELECTRIC CURRENTS; GATE DIELECTRICS; MATHEMATICAL MODELS; SILICON; THICKNESS MEASUREMENT;

COMPACT MODELING; DOUBLE GATE CURRENT MODELING; KWD SHORT CHANNEL EFFECTS; TRANSCENDENTAL EQUATIONS;

MOSFET DEVICES;

EID: 44749087259     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2008.03.009     Document Type: Article

References (12)

1. Colinge J.P. Silicon-on-insulator technology: materials to VLSI. 3rd ed. (2004), Kluwer Academic Publishers
2. Int. Tech. Roadmap for Semiconductors; 2007; [available online www.itrs.net].
3. Li Y., and Chou H.M. A comparative study of electrical characteristic on sub-10-nm double-gate MOSFETs. IEEE Trans Nanotechnol 4 5 (2005) 645-647
4. Ortiz-Conde A., García-Sánchez F.A., Muci J., Malobabic S., and Liou J.J. A review of core compact models for undoped double-gate SOI MOSFETs. IEEE Trans Electron Dev 54 Jan (2007) 131-140
5. Song J, Yu B, Xiong W, Hsu CH, Cleavelin CR. MA M, et al. Experimental hardware calibrated compact models fro 50 nm n-channel FinFETs. In: IEEE Int SOI Conference, CA, October 1-4, 2007.
6. Moldovan O., Cerdeira A., Jimenez D., Raskin J.-P., Kilchytska, Flandre D., et al. Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications. Solid-State Electron 51 (2007) 655-661
7. Cerdeira A., Moldovan O., Iñiguez B., and Estrada M. Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs. Solid-State Electron 52 (2008) 830-837
8. Cerdeira A, Moldovan O, Alvarado J, Iñiguez B, Estrada M. Compact model for symmetric doped double-gate MOSFETS including SCE. EUROSOI, 24-26 January 2007, Leuven, Belgium. p. 47-8.
9. Cerdeira A., Iñiguez B., and Estrada M. Improved compact model for symmetric doped double-gate MOSFETs, SBMicro 2007. ECS Trans 9 1 (2007) 47-56 Rio de Janeiro, Brazil, September 2007
10. Device simulator ATLAS, Silvaco International; 2007.
11. Susuki K., Tanaka T., Tosaka Y., Horie H., and Arimoto Y. Scaling theory for double-gate SOI MOSFETs. IEEE Trans Electron Dev 40 12 (1993) 2326-2329
12. Prégaldiny F., Krummenacher, Sallese J.-M., Diagne, and Lallement. An explicit quasi-static charge-based compact model for symmetric DG MOSFET. NSTI-Nanotech 2006 3 (2006) 686-691