Experimental hardware calibrated compact models for 50nm n-channel FinFETs

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2007, Pages 131-132

  Song, Jooyoung ^a   Yu, Bo ^a   Xiong, W ^b   Hsu, C H ^c   Cleavelin, C R ^b   Ma, M ^c   Patruno, P ^d   Taur, Yuan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^d PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPACT MODELS; MOBILITY MODEL; SHORT CHANNEL EFFECTS; TRANSPORT EFFECTS;

ELECTRIC CURRENTS; ELECTRON MOBILITY; ELECTRON TRANSPORT PROPERTIES; MATHEMATICAL MODELS;

FIELD EFFECT TRANSISTORS;

EID: 43549091305     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2007.4357887     Document Type: Conference Paper

References (5)

1. G.D.J.Smit et al., IEDM06, pp. 175-178, 2006.
2. H.Lu, "Compact Modeling of Double-Gate MOSFETs", Ph.D. dissertation, UCSD, 2006.
3. W.Wang, "Compact Modeling of Quantum Effects in Double-Gate MOSFETs", Ph.D. dissertation, UCSD, 2007.
4. Y.Taur and T.H.Ning, "Fundamentals of Modern VLSI Devices", Cambridge University Press, 1998.
5. X. Liang and Y. Taur, IEEE TED 51, pp. 1385-1391, 2004.