A 6-10 bits reconfigurable 20MS/s digitally enhanced pipelined ADC for multi-standard wireless terminals

ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

Volumn , Issue , 2006, Pages 496-499

  Audoglio, Walter ^a   Zuffetti, Everest ^a   Cesura, Giovanni ^a   Castello, Rinaldo ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BACKGROUND DIGITAL CALIBRATION; OP-AMP SHARING TECHNIQUES; TEST CHIP;

ELECTRIC POWER UTILIZATION; OPTICAL RESOLVING POWER; SILICON; WIRELESS NETWORKS;

ANALOG TO DIGITAL CONVERSION;

EID: 46749111189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2006.307498     Document Type: Conference Paper

References (3)